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參數(shù)資料
| 型號(hào)： | AD8600CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Channel, 8-Bit Multiplying DAC |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 2 us SETTLING TIME, 8-BIT DAC, UUC43 |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 236K |
| 代理商： | AD8600CHIPS |
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Parameter
Symbol
Condition
Min
T yp
Max
Units
ST AT IC PERFORMANCE
1
Resolution
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Voltage
Full-Scale Voltage Error
Full-Scale T empco
Zero Scale Error
Zero Scale Error
Zero Scale Error
Zero Scale T empco
Reference Input Resistance
Reference Input Capacitance
2
N
T UE
INL
DNL
V
FS
V
FSE
T CV
FS
V
ZSE
V
ZSE
V
ZSE
T CV
ZS
R
REF
C
REF
8
–1
–1
–1
3.473
–1
Bits
LSB
LSB
LSB
V
LSB
ppm/
°
C
mV
LSB
LSB
μ
V/
°
C
k
pF
All Other DACs Loaded with Data = 55
H
±
3/4
±
1/2
±
1/4
3.486
+1
+1
+1
3.500
+1
Guaranteed Monotonic
Data = FF
H
, V
REF
= +3.5 V
Data = FF
H
, V
REF
= +3.5 V
Data = FF
H
, V
REF
= +3.5 V
Data = 00
H
,
RS
= “0,” T
A
= +25
°
C
Data = 00
H
, All Other DACs Data = 00
H
Data = 00
H
, All Other DACs Data = 55
H
Data = 00
H
, V
CC
= +5 V, V
EE
= –5 V
Data = AB
H
Data = AB
H
±
20
±
1
–2
–1
+2
+1
±
1/2
±
10
2
1.2
240
ANALOG OUT PUT
Output Voltage Range
Output Voltage Range
2
Output Current
Capacitive Load
2
OVR
1
OVR
2
I
OUT
C
L
V
REF
= +3.5 V
V
CC
= V
DD2
= +7 V, V
EE
= –0.7 V, V
REF
= 5 V
Data = 80
H
No Oscillation
0.000
0.000
3.500
5.000
V
V
mA
pF
±
2
50
LOGIC INPUT S
Logic Input Low Voltage
Logic Input High Voltage
Logic Input Current
Logic Input Capacitance
2
V
IL
V
IH
I
IL
C
IL
0.8
V
V
μ
A
pF
2.4
10
10
LOGIC OUT PUT S
Logic Out High Voltage
Logic Out Low Voltage
V
OH
V
OL
I
OH
= –0.4 mA
I
OL
= 1.6 mA
3.5
V
V
0.4
AC CHARACT ERIST ICS
2
Reference In Bandwidth
Slew Rate
Voltage Noise Density
Digital Feedthrough
Voltage Output Settling T ime
3
Voltage Output Settling T ime
3
BW
SR
e
N
FT
t
S1
t
S2
–3 dB Frequency, V
REF
= 2.5 V
DC
+ 0.1 V
AC
For
V
REF
or FS Code Change
f = 1 kHz, V
REF
= 0 V
Digital Inputs to DAC Outputs
±
1 LSB of Final Value, FS Data Change
±
1 LSB of Final Value,
V
REF
= 1 V, Data = FF
H
500
4
kHz
V/
μ
s
nV/
√
Hz
nVs
μ
s
μ
s
7
46
10
1
1
2
2
POWER SUPPLIES
Positive Supply Current
Negative Supply Current
Logic Supply Currents
Power Dissipation
4
Power Supply Sensitivity
Logic Power Supply Range
Pos Power Supply Range
2
Neg Power Supply Range
2
I
CC
I
EE
I
DD1&2
P
DISS
PSS
V
DDR
V
CCR
V
EER
V
IH
= 5 V, V
IL
= 0 V, V
EE
= –5 V, No Load
V
IH
= 5 V, V
IL
= 0 V, V
EE
= –5 V, No Load
V
IH
= 5 V, V
IL
= 0 V, V
EE
= –5 V, No Load
V
IH
= 5 V, V
IL
= 0 V, V
EE
= –5 V, No Load
V
CC
&
V
EE
=
±
5%
22
22
35
35
0.1
350
0.007
5.25
7.0
0.0
mA
mA
mA
mW
%/%
V
V
V
225
4.75
V
DD
–5.25
NOT ES
1
When V
REF
= +3.500 V, 1 LSB = 13.67 mV.
2
Guaranteed by design not subject to production test.
3
Settling time test is performed using R
L
= 50 k
and C
L
= 35 pF.
4
Power Dissipation is calculated using 5 V
×
(I
DD
+ |I
SS
| + I
DD1
+ I
DD2
).
Specifications subject to change without notice.
DUAL SUPPLY
(@ V
DD1
= V
DD2
= V
CC
= +5V
±
5%, V
EE
= –5V
±
5%, V
REF
= +3.500V, –40
°
C
≤
T
A
≤
+85
°
C, unless otherwse noted)
AD8600
REV. 0
–3–
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