參數(shù)資料
型號(hào): AD823AARZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP FET RR 17MHZ DUAL 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: J-FET
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 35 V/µs
-3db帶寬: 19MHz
電流 - 輸入偏壓: 1.3pA
電壓 - 輸入偏移: 700µV
電流 - 電源: 6.3mA
電流 - 輸出 / 通道: 44mA
電壓 - 電源,單路/雙路(±): 3 V ~ 36 V,±1.5 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
AD823A
Data Sheet
Rev. | Page 14 of 20
THEORY OF OPERATION
The AD823A is a dual voltage feedback amplifier with an
N-channel JFET input stage and a rail-to-rail bipolar output
stage. It is fabricated on the Analog Devices, Inc. XFCB process,
a dielectrically isolated complementary bipolar process featuring
high speed 36 V bipolar devices along with JFETs and thin film
resistors. The N-channel input stage handles signals up to 200 mV
below the negative supply while maintaining picoamp level
input currents. The rail-to-rail output maximizes the amplifier’s
output range and can provide up to 40 mA linear drive current
with output voltages within .5 V of either power rail. Laser-
trimmed thin film resistors are used to optimize offset voltage
(3.5 mV max over the entire supply range) and offset voltage
drift (typical 1 uV/°C).
Figure 38 shows the architecture of an amplifier. Two stages are
used, with the first stage folded cascode input driving the
differential input of the second stage output. The voltage swing
at nodes S1p and S1n are kept small to minimize the generation
of nonlinear currents due to junction capacitances. This improves
distortion performance. Inputs and outputs of the amplifier are
fully protected with dedicated ESD diodes.
OUTPUT IMPEDANCE
The low frequency open-loop output impedance of the common-
emitter output stage used in this design is approximately 50 k.
Although this is significantly higher than a typical emitter follower
output stage, when it is connected with feedback, the open-loop
gain of the op amp reduces the output impedance.
With 105 dB of open-loop gain, the output impedance is reduced
to <0.01 . At higher frequencies, the output impedance rises as
the open-loop gain of the op amp drops; however, the output also
becomes capacitive due to the integrator capacitor. This
prevents the output impedance from ever becoming excessively
high (see Figure 21), which can cause stability problems when
driving capacitive loads. In fact, the AD823A has excellent
capacitive load drive capability for a high frequency op amp.
Figure 36 shows the results of the AD823A connected as a
follower while driving a 470 pF direct capacitive load. Under
these conditions, the phase margin is approximately 35°. For a
greater phase margin, use a low value resistor in series with the
output to decouple the effect of the load capacitance from the
op amp (see Figure 28). In addition, running the part at higher
gains also improves the capacitive load drive capability of the
op amp.
09439-
138
+VS
–IN
+IN
OUT
–VS
VBIAS
S1P
S1N
OUTPUT
DRIVE
Figure 38. Simplified Schematic
B
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