參數(shù)資料
型號: AD823AARZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 11/20頁
文件大小: 0K
描述: IC OPAMP FET RR 17MHZ DUAL 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: J-FET
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 35 V/µs
-3db帶寬: 19MHz
電流 - 輸入偏壓: 1.3pA
電壓 - 輸入偏移: 700µV
電流 - 電源: 6.3mA
電流 - 輸出 / 通道: 44mA
電壓 - 電源,單路/雙路(±): 3 V ~ 36 V,±1.5 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
Data Sheet
AD823A
Rev. | Page 19 of 20
MAXIMIZING PERFORMANCE THROUGH PROPER
LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD823A, care
should be taken in the circuit board layout. The PCB surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier, reducing
parasitic resistance on the board. The use of guard rings around the
amplifier inputs further reduces leakage currents. Figure 48 shows
how the guard rings should be configured, and Figure 49 shows
the top view of how a surface-mount layout can be arranged. The
guard ring does not need to be a specific width, but it should form
a continuous loop around both inputs. By setting the guard ring
voltage equal to the voltage at the non-inverting input, parasitic
capacitance is minimized as well. For further reduction of leakage
currents, components can be mounted to the PCB using Teflon
standoff insulators.
VOUT
VIN
AD823A
VIN
AD823A
VIN
AD823A
09439-
152
Figure 48. Guard Ring Layout and Connections to
Reduce PCB Leakage Currents
V–
V+
VREF
VIN1
VIN2
GUARD
RING
R1
R2
R1
AD823A
GUARD
RING
09439-
153
Figure 49. Top View of AD823A SOIC Layout with Guard Rings
B
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