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參數(shù)資料
| 型號： | AD8231WACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP INST RRO 2.7MHZ 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 1.1 V/µs |
| 增益帶寬積： | 7MHz |
| 電流 - 輸入偏壓： | 250pA |
| 電壓 - 輸入偏移： | 4µV |
| 電流 - 電源： | 4mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 6 V，±1.5 V ~ 3 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ EP（4x4） |
| 包裝： | 帶卷 (TR) |
AD8231
Rev. B | Page 22 of 24
When operating the AD8231 on dual supplies, a level-shift is
typically needed from standard single-supply control logic. One
easy way to accomplish the level-shift is through a single-pole,
application schematic for ±2.5 V operation.
0658
6-
0
55
+2.5V
–2.5V
+2.5V
–2.5V
+2.5V
–2.5V
A0
A1
A2
EN
VDD
GND
VSS
–2.5V
GND
VDD
DIGITAL
CONTROL
(FPGA,
MICROCONTROLLER,
ETC.)
VDIGITAL
ADG633
AD8231
A0 A1 A2
+VS
–VS
SDN
CS
+2.5V
VDIGITAL IS THE DIGITAL SUPPLY VOLTAGE. IT CAN BE
ANY VOLTAGE BETWEEN 2.5V AND 9.5V.
–2.5V
Figure 55. Converting Single-Supply Control Signals to Dual Supply.
SALLEN KEY FILTER
The extra op amp in the AD8231 can be used to create a 2-pole
Sallen Key filter. Such a filter can remove excess noise or
perform antialiasing before an analog-to-digital converter.
Figure 56 shows how to create a 2-pole low-pass Butterworth
filter. Components R1, R2, C1, and C2 set the frequency of the
filter. The ratio of R3 and R4 sets the peaking of the filter. If R4
equals 10 kΩ, R3 should equal 5.9 kΩ for an optimum 2-pole
response.
Depending on the circuitry before and after the AD8231,
a 3-pole filter can be possible. If the previous stage has a small
output impedance, an additional pole can be added before the
in amp (R6, R7, and C4). If the following stage has a high input
impedance, an additional pole can be added after the op amp
(R5 and C3). Peaking from the Sallen Key stage should be
higher to compensate for the extra attenuation of the third pole;
both R3 and R4 should be 10 kΩ for optimum response.
Note that in addition to setting the peaking of the filter, the
ratio R3/R4 also sets the dc gain: G = 1 + R3/R4. If lower dc
gain is required, replace R1 with a voltage divider, where the
output resistance of the divider is equal to the required value of R1.
Figure 56 shows a bias point connected to R4 and the in-amp
reference. The filter stage amplifies the signal around this bias
point. The bias point is ypically midsupply and should be low
impedance.
Table 10. Recommended Component Values for Butterworth
Low-Pass Filter in Figure 56
Optional Poles
Sallen Key
Before In-Amp
After Op Amp
3 dB
Freq
R1, R2
(kΩ)
C1, C2
(nF)
R6, R7
(kΩ)
C4
(nF)
R5
(kΩ)
C3
(nF)
32 Hz
499
10
499
4.7
49.9
100
100 Hz
158
10
158
4.7
16
100
320 Hz
49.9
10
49.9
4.7
4.99
100
1 kHz
158
1
158
0.47
1.6
100
3.2 kHz
49.9
1
49.9
0.47
0.499
100
10 kHz
15.8
1
15.8
0.47
0.16
100
32 kHz
4.99
1
4.99
0.47
0.049
100
06
58
6-
0
56
IN-AMP
OP AMP
REF
BIAS
POINT
BIAS
POINT
R7
R1
R2
R6
R5
C4
SALLEN KEY
(TWO POLE)
OPTIONAL POLE
C3
R3
R4
C2
C1
Figure 56. Butterworth Low-Pass Filter (Dotted Sections Indicate Optional Poles)
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