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參數資料
| 型號： | AD8231WACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP INST RRO 2.7MHZ 16LFCSP |
| 標準包裝： | 5,000 |
| 放大器類型： | 儀表 |
| 電路數： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉換速率： | 1.1 V/µs |
| 增益帶寬積： | 7MHz |
| 電流 - 輸入偏壓： | 250pA |
| 電壓 - 輸入偏移： | 4µV |
| 電流 - 電源： | 4mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 6 V，±1.5 V ~ 3 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP-VQ EP（4x4） |
| 包裝： | 帶卷 (TR) |
AD8231
Rev. B | Page 18 of 24
THEORY OF OPERATION
–INB
OUTB
+INB
OUTA
–INA
+INA
REF
–VS
+VS
CS
A0
A1
A2
SDN
AD8231
A1
A3
A4
14k
A2
0
65
86
-0
31
Figure 49. Simplified Schematic
AMPLIFIER ARCHITECTURE
The AD8231 is based on the classic 3-op amp topology. This
topology has two stages: a preamplifier to provide amplification,
followed by a difference amplifier to remove the common-mode
voltage. Figure 49 shows a simplified schematic of the AD8231.
The preamp stage is composed of Amplifier A1, Amplifier A2,
and a digitally controlled resistor network. The second stage is a
gain of 1 difference amplifier composed of Amplifier A3 and
four 14 kΩ resistors. A1, A2, and A3 are all zero drift, rail-to-
rail input, rail-to rail-output amplifiers.
The AD8231 design makes it extremely robust over temperature.
The AD8231 uses an internal thin film resistor to set the gain.
Because all of the resistors are on the same die, gain temperature
drift performance and CMRR drift performance are better than
can be achieved with topologies using external resistors. The
AD8231 also uses an auto-zero topology to null the offsets of all its
internal amplifiers. Because this topology continually corrects for
any offset errors, offset temperature drift is nearly nonexistent.
The AD8231 also includes a free operational amplifier. Like
the other amplifiers in the AD8231, it is a zero drift, rail-to-rail
input, rail-to-rail output architecture.
GAIN SELECTION
The gain of the AD8231 is set by voltages applied to the A0, A1,
and A2 pins. To change the gain, the CS pin must be driven
low. When the CS pin is driven high, the gain is latched, and
voltages at the A0 to A2 pins have no effect. Because the CS pin
is level sensitive rather than edge sensitive, it can also be tied
permanently low.
shows the different gain settings.
The time required for a gain change is dominated by the settling
time of the amplifier. The AD8231 takes about 200 ns to switch
gains, after which the amplifier begins to settle. Refer to Figure 28
through Figure 32 to determine the settling time for different gains.
Table 7. Truth Table for AD8231 Gain Settings
CS
A2
A1
A0
Gain
Low
1
Low
High
2
Low
High
Low
4
Low
High
8
Low
High
Low
16
Low
High
Low
High
32
Low
High
Low
64
Low
High
128
High
X
No change
REFERENCE TERMINAL
The output voltage of the AD8231 is developed with respect to
the potential on the reference terminal, which is useful when
the output signal needs to be offset to a midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8231 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or VS by more than 0.3 V.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 49, the reference
terminal, REF, is at one end of a 14 kΩ resistor. Additional
impedance at the REF terminal adds to this 14 kΩ resistor
and results in amplification of the signal connected to the
positive input, causing a CMRR error.
INCORRECT
AD8231
IN-AMP
VREF
CORRECT
AD8231
IN-AMP
VREF
AD8231
OP AMP
+
–
+
–
+
–
06
58
6-
0
32
REF
Figure 50. Driving the Reference (REF)
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