
Data Sheet
AD8195
Rev. B | Page 3 of 20
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AMUXVCC = 5 V, VREF_IN = 5 V, VREF_OUT = 5 V, AVEE = 0 V, differential input
swing = 1000 mV, TMDS outputs terminated with external 50 resistors to 3.3 V, unless otherwise noted.
TMDS PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
TMDS DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
NRZ
2.25
Gbps
Bit Error Rate (BER)
PRBS 223 1
109
Added Data Jitter
DR ≤ 2.25 Gbps, PRBS 27 1
31
ps p-p
Added Clock Jitter
1
ps rms
Differential Intrapair Skew
At output
1
ps
Differential Interpair Skew
At output
30
ps
TMDS EQUALIZATION PERFORMANCE
Boost frequency = 1.5 GHz
12
dB
Boost frequency = 1.5 GHz
6
dB
TMDS INPUT CHARACTERISTICS
Input Voltage Swing
Differential
150
1200
mV
Input Common-Mode Voltage (VICM)
AVCC 800
AVCC
mV
TMDS OUTPUT CHARACTERISTICS
High Voltage Level
Single-ended, high speed channel
AVCC 200
AVCC + 10
mV
Low Voltage Level
Single-ended, high speed channel
AVCC 600
AVCC 400
mV
Rise/Fall Time (20% to 80%)
3DR = 2.25 Gbps
50
90
150
ps
TMDS TERMINATION
Input Termination Resistance
Single-ended
50
Output Termination Resistance
Single-ended
50
1
Output meets transmitter eye diagram as defined in the DVI Standard Revision 1.0 and HDMI Standard.
2
Cable output meets receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and HDMI Standard.
3
Output rise/fall time measurement excludes external components, such as HDMI connector or external ESD protection diodes. See th
e Applications Informationsection for more information.