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參數(shù)資料
| 型號： | AD8193ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH TMDS BUFF 2:1 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 開關(guān) |
| 電路： | 1 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 托盤 |
AD8193
Rev. 0 | Page 12 of 16
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty
cycle distortion (DCD). The p and n of a given differential pair
should always be routed together to establish the required 100 Ω
differential impedance. Enough space should be left between
the differential pairs of a given group so that the n of one pair
does not couple to the p of another pair. For example, one tech-
nique is to make the interpair distance 4 to 10 times wider than
the intrapair spacing.
Any group of four TMDS channels (Input A, Input B, or the
output) should have closely matched trace lengths to minimize
interpair skew. Severe interpair skew can cause the data on the
four different channels of a group to arrive out of alignment
with one another. A good practice is to match the trace lengths
for a given group of four channels to within 0.05 inches on FR4
material.
The length of the TMDS traces should be minimized to reduce
overall signal degradation. Commonly used PC board material
such as FR4 is lossy at high frequencies; therefore, long traces
on the circuit board increase signal attenuation, resulting in
decreased signal swing and increased jitter through intersymbol
interference (ISI).
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on a
number of variables, including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask.
There are many combinations that can produce the correct
characteristic impedance. It is generally required to work with
the PC board fabricator to obtain a set of parameters to produce
the desired results.
To guarantee a differential pair with a differential impedance of
100 Ω over the entire length of the trace, change the width of
the traces in a differential pair based on how closely one trace is
coupled to the other. When the two traces of a differential pair
are close and strongly coupled, they should have a width that
produces a 100 Ω differential impedance. When the traces split
apart to go into a connector, for example, and are no longer so
strongly coupled, the width of the traces should be increased to
yield a differential impedance of 100 Ω in the new configuration.
Ground Current Return
In some applications, it may be necessary to invert the output
pin order of the AD8193. This requires routing the TMDS
traces on multiple layers of the PCB. When routing differential
pairs on multiple layers, it is also necessary to reroute the
corresponding reference plane to provide one continuous
ground current return path for the differential signals. Standard
plated through-hole vias are acceptable for both the TMDS
traces and the reference plane. An example of this is illustrated
in Figure 21.
PCB DIELECTRIC
SILKSCREEN
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
LAYER 4: SIGNAL (MICROSTRIP)
THROUGH-HOLE VIAS
LAYER 1: SIGNAL (MICROSTRIP)
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
LAYER 3: PWR
(REFERENCE PLANE)
07
00
3-
02
2
Figure 21. Example Routing of Reference Plane
TMDS Terminations
The AD8193 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. The termination
resistors back-terminate the output TMDS transmission lines.
These back-terminations act to absorb reflections from imped-
ance discontinuities on the output traces, improving the signal
integrity of the output traces and adding flexibility to how the
output traces can be routed. For example, interlayer vias can be
used to route the AD8193 TMDS outputs on multiple layers of the
PCB without severely degrading the quality of the output signal.
In a typical application, the AD8193 output is connected to an
HDMI/DVI receiver or to another device with a 50 Ω single-ended
input termination. It is recommended that the outputs be
terminated with external 50 Ω on-board resistors when the
AD8193 is not connected to another device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD8193ACPZ-R7 | 功能描述:IC SWITCH TMDS BUFF 2:1 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| AD8193-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Buffered 2:1 TMDS Switch |
| AD8194ACPZ | 功能描述:IC TMDS SWITCH BUFF 2:1 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤 |
| AD8194ACPZ-R7 | 功能描述:IC SWITCH TMDS BUFF 2:1 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| AD8194-EVALZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD8194 - Bulk |
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