參數(shù)資料
型號: AD8159ASVZ
廠商: Analog Devices Inc
文件頁數(shù): 6/24頁
文件大?。?/td> 0K
描述: IC MUX/DEMUX QUAD BUFF 100TQFP
標(biāo)準(zhǔn)包裝: 1
系列: XStream™
應(yīng)用: 2:1 多路復(fù)用器/1:2 多路分配器
接口: 串行
電源電壓: 3 V ~ 3.6 V
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 管件
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 801 (CN2011-ZH PDF)
AD8159
Rev. B | Page 14 of 24
TEST CIRCUITS
All graphs were generated using the setup shown in Figure 31, unless otherwise specified.
05
61
1-
03
0
0.25"
TERADYNE FR4 TEST BACKPLANE
DIFFERENTIAL STRIPLINE TRACES
8mm WIDE, 8mm SPACE, 8mm HEIGHT
TRACE LENGTHS = 6", 18", 24", 30" + 3" × 2 DAUGHTER CARDS
GBX4 TO SMA DAUGHTER CARDS
Figure 30. Test Backplane
05
61
1-
03
1
A
B
C
A
B
AD8159
AC-COUPLED
EVALUATION BOARD
TEST BACKPLANE
50
HIGH SPEED
REAL-TIME
OSCILLOSCOPE
50
50 CABLE
PATTERN
GENERATOR
DATA OUT
NOTES
1. SINGLE-ENDED REPRESENTATION
Figure 31. AC-Coupled Test Circuit
056
11-
033
A
B
C
A
B
AD8159
AC-COUPLED
EVALUATION BOARD
TEST BACKPLANE
50
50 CABLE
PATTERN
GENERATOR
DATA OUT
HIGH SPEED
REAL-TIME
OSCILLOSCOPE
50
A
B
C
A
B
AD8159
AC-COUPLED
EVALUATION BOARD
50
50 CABLE
NOTES
1. SINGLE-ENDED REPRESENTATION
DEVICE UNDER TEST
Figure 32. Equalization Test Circuit, Test Circuit Used for Figure 19 and Figure 20
05
61
1-
0
34
50 CABLE
PATTERN
GENERATOR
DATA OUT
HIGH SPEED
SAMPLING
OSCILLOSCOPE
50
A
B
C
A
B
AD8159
AC-COUPLED
EVALUATION BOARD
50 CABLE
NOTES
1. SINGLE-ENDED REPRESENTATION
50
Figure 33. Random Jitter Test Circuit, Test Circuit Used for Figure 24
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