
AD8151
Rev. B | Page 16 of 40
02169-031
RESET INPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
tTOD
tTW
Figure 31. Asynchronous Reset
Table 10. Asynchronous Reset
Parameter
Mnemonic
Function
Conditions
Min
Typ
Max
Unit
Disable Time
tTOD
Output disable from reset
TA = 25°C
25
30
ns
Width of Reset Pulse
tTW
VDD = 5 V
15
ns
VCC = 3.3 V
CONTROL INTERFACE PROGRAMMING EXAMPLE
The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock
period t0 is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9.
Table 11. Basic Test Pattern
Vector No.
RESET
CS
WE
RE
UPDATE
A[4:0]
D[6:0]
Comments
0
1
xxxxx
xxxxxxx
Disable all outputs
1
xxxxx
xxxxxxx
2
1
0
1
10001
1000111
All outputs connected to Input 7
3
1
0
1
10001
1000111
Write to first rank
4
1
0
1
10001
1000111
5
1
0
1
10000
1100000
Connects Output 16 to Input 32
6
1
0
1
10000
1100000
Write to first rank
7
1
0
1
10000
1100000
8
1
0
1
0
xxxxx
xxxxxxx
Transfer to second rank
9
1
0
1
xxxxx
xxxxxxx
10
1
xxxxx
xxxxxxx
Disable interface