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參數(shù)資料
| 型號： | AD8151ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 33X17 184LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 33:17 |
| 電壓電源： | 雙電源 |
| 電壓 - 電源，單路/雙路(±)： | ±3 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 184-LQFP |
| 供應(yīng)商設(shè)備封裝： | 184-LQFP（20x20） |
| 包裝： | 托盤 |
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AD8151
Rev. B | Page 22 of 40
Thus, the power dissipation of the high output can be ignored and
the output power dissipation for each output can be assumed to
occur in a single static low output that sinks the full output pro-
grammed current. The voltage across which this current flows can
also vary, depending on the output circuit design and the supplies
that are used for the data path circuitry. In general, however, there
is a voltage difference between a logic low signal and VEE. This is
the drop across which the output current flows. For a worst case,
this voltage can be as high as 3.5 V. Thus, for all outputs enabled
and the programmed output current set to 25 mA, the power
dissipated by the outputs is
P = 3.5 V (25 mA) × 17 = 1.49 W
Heat Sinking
Depending on several factors in its operation, the AD8151 can
dissipate upwards of 2 W or more. The part is designed to
operate without the need for an explicit external heat sink.
However, the package design offers enhanced heat removal via
some of the package pins to the PC board traces. The VEE pins
on the input sides of the package (Pin 1 to Pin 46 and Pin 93 to
Pin 138) have finger extensions inside the package that connect
to the paddle upon which the IC chip is mounted. These pins
provide a lower thermal resistance from the IC to the VEE pins
than other pins that just have a bond wire. As a result, these
pins can be used to enhance the heat removal process from the
IC to the circuit board and ultimately to the ambient. The VEE
pins described earlier should be connected to a large area of
circuit board trace material to take the most advantage of their
lower thermal resistance. If there is a large area available on an
inner layer that is at VEE potential, then vias can be provided
from the package pin traces to this layer.
There should be no thermal-relief pattern when connecting the
vias to the inner layers for these VEE pins. Additional vias in
parallel and close to the pin leads can provide an even lower
thermal resistive path. If possible, use 2 oz copper foil to
provide better heat removal than 1 oz copper foil. The AD8151
package has a specified thermal impedance θJA of 30°C/W. This
is the worst case still-air value that can be expected when the
circuit board does not significantly enhance the heat removal
from the package. By using the concept described earlier or by
using forced-air circulation, the thermal impedance can be
lowered.
For an extreme worst case analysis, the junction temperature
increase above the ambient can be calculated assuming 2 W of
power dissipation and a θJA of 30°C/W to yield a 60°C rise above
the ambient. There are many techniques described earlier that
can mitigate this situation. Most actual circuits do not result in
this high an increase of the junction temperature above the
ambient.
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