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參數(shù)資料
| 型號： | AD8151ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/40頁 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWIT 33X17 184LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 33:17 |
| 電壓電源： | 雙電源 |
| 電壓 - 電源，單路/雙路(±)： | ±3 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 184-LQFP |
| 供應(yīng)商設(shè)備封裝： | 184-LQFP（20x20） |
| 包裝： | 托盤 |
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AD8151
Rev. B | Page 21 of 40
Data Path Supplies
The data path supplies have more options for their voltage levels.
The choices here affect several other areas, such as power
dissipation, bypassing, and common-mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is VCC (Pin 41, Pin 98, Pin 149, and Pin 171). The more negative
supply is VEE, which appears on many pins that are not listed here.
The maximum allowable voltage across these supplies is 5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL or PECL. For ECL operation,
VCC is at ground potential, while VEE is at a negative supply
between –3.3 V to –5 V. This makes the common-mode voltage
of the inputs and outputs a negative voltage (see Figure 39).
02169-039
VCC
VDD
VEE
VSS
DATA
PATHS
CONTROL
LOGIC
+3.3V TO +5V
–3.3V TO –5V
GND
0.1
μF
0.1
μF
(ONE FOR EVERY TWO VEE PINS)
AD8151
Figure 39. Power Supplies and Bypassing for ECL Operation
The proper way to run the device is to dc-couple the data paths
to other ECL logic devices that use ground as the most positive
supply and use a negative voltage for VEE. However, if the part is
to be ac-coupled, it is not necessary to have the input/output
common mode at the same level as the other system circuits,
but it is probably more convenient to use the same supply rails
for all devices. For PECL operation, VEE is at ground potential
and VCC is a positive voltage from 3.3 V to 5 V. Thus, the
common mode of the inputs and outputs is at a positive voltage.
These can then be dc-coupled to other PECL operated devices.
If the data paths are ac-coupled, then the common-mode levels
do not matter (see Figure 40).
02169-040
DATA
PATHS
CONTROL
LOGIC
VCC
VDD
VEE
VSS
0.1
μF
0.1
μF
(ONE FOR EACH VCC PIN,
4 REQUIRED)
+3.3V TO +5V
GND
AD8151
Figure 40. Power Supplies and Bypassing for PECL Operation
POWER DISSIPATION
For analysis, the power dissipation of the AD8151 can be
divided into three separate parts. These are the control logic,
the data path circuits, and the (ECL or PECL) outputs, which
are part of the data path circuits but can be dealt with
separately. The control logic is CMOS technology and does not
dissipate a significant amount of power. This power is, of
course, greater when the logic supply is 5 V rather than 3 V, but
overall it is not a significant amount of power and can be
ignored for thermal analysis.
02169-041
DATA
PATHS
CONTROL
LOGIC
VCC
VDD
VEE
IOUT
ROUT
VOUT LOW – VEE
VSS
GND
AD8151
I, DATA PATH
LOGIC
Figure 41. Major Power Consumption Paths
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
is constant, so operating at a lower voltage can decrease power
dissipation by about 35 percent. The power dissipated in the
data path outputs is affected by several factors. The first is
whether the outputs are enabled or disabled. The worst case
occurs when all of the outputs are enabled. The current
consumed by the data path logic can be approximated by
ICC = 35 mA + [IOUT/20 mA × 3 mA)] × (no. of outputs enabled)
This equation states that a minimum ICC of 35 mA always flows.
ICC increases by a factor that is proportional to both the number
of enabled outputs and the programmed output current.
The power dissipated in this circuit section is simply the voltage
of this section (VCC – VEE) times the current. To calculate the
worst case, assume that VCC – VEE is 5.0 V, all outputs are
enabled, and the programmed output current is 25 mA. The
power dissipated by the data path logic is
P = 5.0 V {35 mA + [4.5 mA + (25 mA/20 mA × 3 mA)] × 17} = 876 mW
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to VEE, and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair is low and draws the full output current
(and dissipates most of the power for that output), while the
complementary output of the pair is high and draws insignifi-
cant current.
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