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參數(shù)資料
| 型號(hào)： | AD8124ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC HS RCVR EQUALIZER 40VFQFN |
| 標(biāo)準(zhǔn)包裝： | 42 |
| 類型： | 接收器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 3/3 |
| 電源電壓： | ±4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
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AD8124
Rev. 0 | Page 14 of 16
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
A suitable filter that uses a surface-mount ferrite bead is shown
Because the frequency response was taken using a 50 Ω network
analyzer and with only one 0.1 μF capacitor on the AD8124 side,
the actual amount of rejection provided by the filter in a real-world
application is different from that shown in Figure 28. The general
shape of the rejection curve, however, matches Figure 28, providing
substantially increased overall PSRR from approximately 5 MHz to
500 MHz, where it is most needed. One filter is required on each
of the two supplies (not one filter per supply pin).
Standard high speed PCB layout practices should be adhered
to when designing with the AD8124. A solid ground plane is
required and controlled impedance traces should be used when
interconnecting the high speed signals. Source termination resistors
on all outputs must be placed as close as possible to the output pins.
The exposed paddle on the underside of the AD8124 must be
connected to a pad that connects to at least one PCB plane.
Several thermal vias should be used to make the connection
between the pad and the plane(s).
FAIR-RITE
2743021447
*ALL AD8124 SUPPLY PINS ARE INDIVIDUALLY
DECOUPLED WITH A 0.1F CAPACITOR.
0.1F
4700pF
SYSTEM
SUPPLY
TO AD8124*
09
60
1
-02
7
High quality 0.1 μF power supply decoupling capacitors should
be placed as close as possible to all supply pins. Small surface-
mount ceramic capacitors should be used, and tantalum capacitors
are recommended for bulk supply decoupling.
Figure 27. Power Supply Filter
POWER-DOWN
–120
–100
–80
–60
–40
–20
0
10k
100k
1M
10M
100M
FREQUENCY (Hz)
O
U
T
P
UT
RE
S
P
O
NS
E
(d
B)
0960
1-
028
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. The input
logic levels and supply current in power-down mode are presented
in the Power Supply section of Table 1.
Figure 28. Power Supply Filter Frequency Response in a 50 Ω System
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