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參數(shù)資料
| 型號： | AD8124ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HS RCVR EQUALIZER 40VFQFN |
| 標準包裝： | 42 |
| 類型： | 接收器 |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 電源電壓： | ±4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
AD8124
Rev. 0 | Page 11 of 16
APPLICATIONS INFORMATION
BASIC OPERATION
The AD8124 is easy to apply because it contains everything
on-chip needed for cable loss compensation. Figure 19 shows a
basic application circuit (power supplies not shown) with common-
mode sync pulse extraction that is compatible with the common-
mode sync pulse encoding technique used in the AD8134, AD8142,
is not required, the terminations can be single 100 Ω resistors,
and the comparator inputs can be left floating. In Figure 19, the
AD8124 feeds a high impedance input, such as a delay line or
crosspoint switch, and the additional gain of two that makes up
for double termination loss is not required.
COMPARATORS
In addition to general-purpose applications, the two on-chip
comparators can be used to extract video sync pulses from the
received common-mode voltages or to receive differential digital
information. Built-in hysteresis helps to eliminate false triggers
from noise. The Sync Pulse Extraction Using Comparators
section describes the sync extraction details.
The comparator outputs have nearly 0 Ω output impedance and
are designed to drive source-terminated transmission lines. The
source termination technique uses a resistor in series with each
comparator output such that the sum of the comparator source
resistance (≈0 Ω) and the series resistor equals the transmission
line characteristic impedance. The load end of the transmission
line is high impedance. When the signal is launched into the source
termination, its initial value is one-half its source value because its
amplitude is divided by two in the voltage divider formed by the
source termination and the transmission line. At the load, the
signal experiences nearly 100% positive reflection due to the
high impedance load and is restored to nearly its full value. This
technique is commonly used in PCB layouts that involve high
speed digital logic.
Figure 18 shows how to apply the comparators with source
termination when driving a 50 Ω transmission line that is high
impedance at its receive end.
49.9
HIGH-Z
Z0 = 50
09
60
1-
01
8
Figure 18. Using a Comparator with Source Termination
18
RED
BLUE
GREEN
CMV
RED CMV
BLUE CMV
AD8124
15
12
6
4
VPEAK
26
25
27
23
28
VPOLE
VOFFSET
VGAIN
HSYNC OUT
VSYNC OUT
32
31
GREEN
35
34
38
37
3
2
7
8
RECEIVED
RED VIDEO
RECEIVED
GREEN VIDEO
RECEIVED
BLUE VIDEO
RED VIDEO OUT
GREEN VIDEO OUT
BLUE VIDEO OUT
ANALOG
CONTROL
INPUTS
POWER-DOWN
CONTROL
GND REFERENCE
24, 39
PD
1
2
1k
49.9
475
49.9
47pF
0
960
1-
01
9
Figure 19. Basic Application Circuit with Common-Mode Sync Extraction
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