參數(shù)資料
型號： AD8120ACPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 5/16頁
文件大?。?/td> 0K
描述： IC ANLG VIDEO DELAY LINE 32LFCSP
標準包裝： 5,000
類型： 視頻延遲線
應用： HD 視頻
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應商設備封裝： 32-LFCSP-EP（5x5）
包裝： 帶卷 (TR)
Data Sheet
AD8120
Rev. A | Page 13 of 16
SPI Timing
Figure 21 shows the SPI 2-byte timing sequence. Table 11 lists
the timing parameters for SPI.
CS
SCK
SDI/SDO
R/
W
0
C1 C0
X
D5 D4 D3 D2 D1 D0
07839-
005
Figure 21. SPI 2-Byte Timing Sequence
t6
t1
t2
t4 t5
t3
CS
SCK
SDI
R/W
D1
D0
07839-
006
Figure 22. SPI Timing Diagram
Table 11. SPI Timing Parameters
Parameter
Description
t1
Setup time, CS to SCK
t2
Clock pulse high, SCK
t3
Clock pulse low, SCK
t4
Setup time, SDI to SCK
t5
Hold time, SDI to SCK
t6
Hold time, SCK to CS
I2C Timing
Figure 23 shows the I2C 3-byte timing sequence. Table 12 lists
the timing parameters for I2C.
SDA
0 1 1 1 0
0
X
D0
D1
D2
D3
D4
D5
C0
C1
A0
A1
ACK
R/
W
SCL
07839-
007
Figure 23. I2C 3-Byte Timing Sequence
SDA
SCL
t1
t2 t
3
t5
t6
t4
07839-
008
Figure 24. I2C Timing Diagram
Table 12. I2C Timing Parameters
Parameter
Description
t1
Setup time, SDA to SCL
t2
Clock pulse high, SCL
t3
Clock pulse low, SCL
t4
Setup time, SDA (input) to SCL
t5
Hold time, SDA (input) to SCL
t6
Hold time, SCL to SDA
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