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參數(shù)資料
| 型號： | AD8118ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 32X32 304BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 32:32 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 電流 - 電源： | 500mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 304-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 304-BGA（31x31） |
| 包裝： | 散裝 |
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AD8117/AD8118
Rev. A | Page 27 of 36
successive negative transitions of WE while UPDATE is held
high, and then have all the new data take effect when UPDATE
goes low. This technique should be used when programming
the device for the first time after power-up when using parallel
programming.
Reset
When powering up the AD8117/AD8118, it is usually desirable
to have the outputs come up in the disabled state. The RESET
pin, when taken low, causes all outputs to be in the disabled state.
However, the UPDATE signal does not reset all registers in the
AD8117/AD8118. This is important when operating in the
parallel programming mode. Refer to the Parallel Programming
Description section for information about programming internal
registers after power-up. Serial programming programs the entire
matrix each time; therefore, no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix, or the matrix can
enter unknown states. To prevent this, do not apply a logic low
signal to UPDATE initially after power-up. The shift register
should first be loaded with the desired data, and then UPDATE
can be taken low to program the device.
The RESET pin has a 20 kΩ pull-up resistor to VDD that can be
used to create a simple power-up reset circuit. A capacitor from
RESET to ground holds RESET low for some time while the rest
of the device stabilizes. The low condition causes all the outputs
to be disabled. The capacitor then charges through the pull-up
resistor to the high state, thus allowing full programming
capability of the device.
Broadcast
The AD8117/AD8118 logic interface has a broadcast mode, in
which all first rank latches can be simultaneously parallel-
programmed to the same data in one write cycle. This is especially
useful in clearing random first rank data after power-up. To
access the broadcast mode, the part is parallel programmed
using the WE, A0 to A4, D0 to D5, and UPDATE device pins.
The only difference is that the SER/PAR pin is held low, as if
serial programming. By holding CLK high, no serial clocking
occurs, and instead, WE can be used to clock all first rank
latches in the chip at once.
OPERATING MODES
The AD8117/AD8118 has fully differential inputs and outputs.
The inputs and outputs can also be operated in a single-ended
fashion. This presents several options for circuit configurations
that require different gains and treatment of terminations, if
they are used.
Differential Input
Each differential input to the AD8117/AD8118 is applied to a
differential receiver. These receivers allow the user to drive the
inputs with a differential signal with an uncertain common-
mode voltage, such as from a remote source over twisted pair.
The receivers respond only to the difference in input voltages,
and will restore a common-mode voltage suitable for the
internal signal path. Noise or crosstalk that is present in both
inputs is rejected by the input stage, as specified by its common-
mode rejection ratio (CMRR). Differential operation offers a
great noise benefit for signals that are propagated over distance
in a noisy environment.
IN+
VOCM
IN–
RG
RCVR
RF
OUT–
OUT+
TO SWITCH MATRIX
06
36
5-
0
59
Figure 65. Input Receiver Equivalent Circuit
The circuit configuration used by the differential input receivers
is similar to that of several Analog Devices, Inc. general-
purpose differential amplifiers, such as the AD8131. It is a
voltage feedback amplifier with internal gain setting resistors.
The arrangement of feedback makes the differential input
impedance appear to be 5 kΩ across the inputs.
kΩ
5
2
,
=
×
=
G
dm
IN
R
This impedance creates a small differential termination error if
the user does not account for the 5 kΩ parallel element, although
this error is less than 1% in most cases. Additionally, the source
impedance driving the AD8117/AD8118 appears in parallel
with the internal gain-setting resistors, such that there may be a
gain error for some values of source resistance. The AD8117/
AD8118 are adjusted such that its gains are correct when driven
by a back-terminated 75 Ω source impedance at each input
phase (37.5 Ω effective impedance to ground at each input pin,
or 75 Ω differential source impedance across pairs of input
pins). If a different source impedance is presented, the differential
gain of the AD8117/AD8118 can be calculated by
S
G
F
dm
IN
OUT,dm
dm
R
V
G
+
=
,
where:
RG = 2.5 kΩ.
RS is the user single-ended source resistance (such as 37.5 Ω for
a back-terminated 75 Ω source).
RF = 2.538 kΩ for the AD8117 and 5.075 kΩ for the AD8118.
In the case of the AD8117,
S
dm
R
G
+
=
kΩ
5
.
2
kΩ
538
.
2
In the case of the AD8118,
S
dm
R
G
+
=
kΩ
5
.
2
kΩ
075
.
5
When operating with a differential input, care must be taken to
keep the common mode, or average, of the input voltages within
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