參數(shù)資料
型號(hào)： AD80066KRSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 0K
描述： IC DSP CTLR 16BIT 28SSOP
標(biāo)準(zhǔn)包裝： 47
類型： 信號(hào)處理器
輸入類型： 模擬
輸出類型： 數(shù)字
接口： 串行
電流 - 電源： 95mA
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
AD80066
Rev. A | Page 17 of 20
CIRCUIT OPERATION
ANALOG INPUTS—CDS MODE
Figure 17 shows the analog input configuration for the CDS
mode of operation. Figure 18 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage that represents the difference between the two
sampled levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1 μF
input capacitor, level-shifting the CCD signal into the input
common-mode range of the AD80066. The time constant of the
input clamp is determined by the internal 5 kΩ resistance and
the external 0.1 μF input capacitance.
AD80066
S1
S2
2pF
S3
2pF
CML
AVDD
S4
5k
1.7k
OFFSET
CIN
0.1F
CCD SIGNAL
0.1F
1F
+
3V
2.2k
6.9k
VINA
0
85
52
-01
7
Figure 17. CDS Mode Input Configuration (All Four Channels Are Identical)
CDSCLK1
CDSCLK2
Q3
(INTERNAL)
S1, S4 CLOSED
S2 CLOSED
S3 CLOSED
S3 OPEN
S2 OPEN
S1, S4 OPEN
08
55
2-
0
18
Figure 18. CDS Mode Internal Switch Timing
EXTERNAL INPUT COUPLING CAPACITORS
The recommended value for the input coupling capacitors is
0.1 μF. Although it is possible to use a smaller capacitor, this
larger value is preferable for several reasons:
Signal attenuation: The input coupling capacitor creates
a capacitive divider using the input capacitance from an
integrated CMOS circuit, which, in turn, attenuates the
CCD signal level. CIN should be large relative to the 10 pF
input capacitance of the IC in order to minimize this effect.
Linearity: Some of the input capacitance of a CMOS IC is
junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, the
attenuation of the CCD signal varies nonlinearly with signal
level. This degrades the system linearity performance.
Sampling errors: The internal 2 pF sampling capacitors retain
a memory of the previously sampled pixel. There is a charge
redistribution error between CIN and the internal sample
capacitors for larger pixel-to-pixel voltage swings. As the
value of CIN is reduced, the resulting error in the sampled
voltage increases. With a CIN value of 0.1 μF, the charge
redistribution error is less than 1 LSB for a full-scale, pixel-
to-pixel voltage swing.
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