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| 型號： | AD7999YRJZ-1RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 4CH I2C SOT23-8 |
| 產(chǎn)品變化通告： | AD7991,5,9 Offset Error Change 17/Sept/2010 |
| 設(shè)計資源： | Using AD8599 as an Ultralow Distortion Driver for the AD7999 (CN0045) |
| 標準包裝： | 10,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 4.68mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
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AD7991/AD7995/AD7999
Rev. B | Page 20 of 28
INTERNAL REGISTER STRUCTURE
CONFIGURATION REGISTER
The configuration register is an 8-bit write-only register that is used to set the operating modes of the AD7991/AD7995/AD7999. The bit
functions are outlined in Table 10. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the
master writes to the AD7991/AD7995/AD7999, the first byte is written to the configuration register.
Table 9. Configuration Register Bit Map and Default Settings at Power-Up
D7
D6
D5
D4
D3
D2
D1
D0
CH3
CH2
CH1
CH0
REF_SEL
FLTR
Bit trial delay
Sample delay
1
0
Table 10. Bit Function Descriptions
Bit
Mnemonic
Comment
D7 to D4
CH3 to CH0
These four channel address bits select the analog input channel(s) to be converted. If a channel address bit
(Bit D7 to Bit D4) is set to 1, a channel is selected for conversion. If more than one channel bit is set to 1, the
AD7991/AD7995/AD7999 sequence through the selected channels, starting with the lowest channel. All
unused channels should be set to 0. Table 11 shows how these four channel address bits are decoded. Prior
to the device initiating a conversion, the channel(s) must be selected in the configuration register.
D3
REF_SEL
This bit allows the user to select the supply voltage as the reference or choose to use an external reference. If
this bit is 0, the supply is used as the reference, and the device acts as a 4-channel input part. If this bit is set
to 1, an external reference must be used and applied to the VIN3/VREF pin, and the device acts as a 3-channel
input part.
D2
FLTR
The value written to this bit of the control register determines whether the filtering on SDA and SCL is
enabled or bypassed. If this bit is set to 0, the filtering is enabled; if it set to 1, the filtering is bypassed.
D1
Bit trial delay
See the Sample Delay and Bit Trial Delay section.
D0
Sample delay
See the Sample Delay and Bit Trial Delay section.
Table 11. Channel Selection
D7
D6
D5
D4
Analog Input Channel1
0
No channel selected
0
1
Convert on VIN0
0
1
0
Convert on VIN1
0
1
Sequence between VIN0 and VIN1
0
1
0
Convert on VIN2
0
1
0
1
Sequence between VIN0 and VIN2
0
1
0
Sequence between VIN1 and VIN2
0
1
Sequence among VIN0, VIN1, and VIN2
1
0
Convert on VIN3
1
0
1
Sequence between VIN0 and VIN3
1
0
1
0
Sequence between VIN1 and VIN3
1
0
1
Sequence among VIN0, VIN1, and VIN3
1
0
Sequence between VIN2 and VIN3
1
0
1
Sequence among VIN0, VIN2, and VIN3
1
0
Sequence among VIN1, VIN2, and VIN3
1
Sequence among VIN0, VIN1, VIN2, and VIN3
1 The AD7991/AD7995/AD7999 converts on the selected channel in the sequence in ascending order, starting with the lowest channel in the sequence.
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