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| 型號： | AD7986BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 2MSPS SAR 20LFCSP |
| 產(chǎn)品培訓模塊： | Motor Control |
| 標準包裝： | 1,500 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 34mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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AD7986
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
REF
2
REF
3
REFGND
4
REFGND
5
IN–
13 CNV
14 SDI
15 TURBO
12 SCK
11 DVDD
6
IN+
7
P
DRE
F
8
VI
O
10
DG
ND
9
S
DO
18
AG
ND
19
BV
DD
20
R
E
FIN
17
AG
ND
16
A
V
DD
TOP VIEW
(Not to Scale)
AD7986
07956-
004
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 2
REF
AI
Reference Output/Input Voltage.
When PDREF = low, the internal reference and buffer are enabled, producing 4.096 V on this pin.
When PDREF = high, the internal reference and buffer are disabled, allowing an externally supplied
voltage reference up to 5.0 V.
Decoupling is required with or without the internal reference and buffer. This pin is referred to the
REFGND pins and should be decoupled closely to the REFGND pins with a 10 F capacitor.
3, 4
REFGND
AI
Reference Input Analog Ground.
5
IN
AI
Differential Negative Analog Input.
6
IN+
AI
Differential Positive Analog Input.
7
PDREF
DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must be used.
8
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, or 2.7 V).
9
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
10
DGND
P
Digital Power Ground.
11
DVDD
P
Digital Power. Nominally at 2.5 V.
12
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
13
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
14
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the
busy indicator feature is enabled.
15
TURBO
DI
Conversion Mode Selection.
When TURBO = high, the maximum throughput (2 MSPS) is achieved. The ADC does not power down
between conversions.
When TURBO = low, the maximum throughput is lower (1.5 MSPS). The ADC powers down between
conversions.
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