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參數(shù)資料
| 型號： | AD7986BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 2MSPS SAR 20LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Motor Control |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 34mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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AD7986
Rev. B | Page 5 of 28
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = 40°C to +85°C, unless otherwise noted.1
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode)
t
CONV
400/500
ns
Acquisition Time
t
ACQ
100
ns
Time Between Conversions (Turbo Mode/Normal Mode)
t
CYC
500/660
ns
CNV Pulse Width (CS Mode)
t
CNVH
10
ns
Data Read During Conversion (Turbo Mode/Normal Mode)
t
DATA
200/300
ns
Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge
t
QUIET
20
ns
SCK Period (CS Mode)
t
SCK
9
ns
SCK Period (Chain Mode)
t
SCK
11
ns
SCK Low Time
t
SCKL
3.5
ns
SCK High Time
t
SCKH
3.5
ns
SCK Falling Edge to Data Remains Valid
t
HSDO
2
ns
SCK Falling Edge to Data Valid Delay
t
DSDO
6
ns
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
t
EN
10
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
8
ns
SDI Valid Setup Time from CNV Rising Edge
t
SSDICNV
4
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
t
HSDICNV
0
ns
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
t
HSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
t
SSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
t
HSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
t
SSDISCK
2
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
t
HSDISCK
3
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
t
DSDOSDI
5
ns
1 See Figure 2 and Figure 3 for load conditions.
500A
IOL
500A
IOH
1.4V
TO SDO
CL
20pF
07956-
002
Figure 2. Load Circuit for Digital Interface Timing
90% VIO
10% VIO
VIH1
VIL1
VIH1
tDELAY
1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
07956-
003
Figure 3. Voltage Levels for Timing
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