參數(shù)資料
型號： AD7938BSUZ-6REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 17/32頁
文件大小： 0K
描述： IC ADC 12BIT 8CHAN 32TQFP
標準包裝： 1
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應商設備封裝： 32-TQFP（7x7）
包裝： 標準包裝
輸入數(shù)目和類型： 8 個單端，單極；4 個差分，單極；4 個偽差分，單極；7 偽差分，單極
產品目錄頁面： 780 (CN2011-ZH PDF)
配用： EVAL-AD7938CBZ-ND - EVAL BOARD FOR AD7938
其它名稱： AD7938BSUZ-6REEL7DKR
AD7938-6
Data Sheet
Rev. C | Page 24 of 32
Reading Data from the AD7938-6
With the W/B pin tied logic high, the AD7938-6 interface operates
in word mode. In this case, a single read operation from the
device accesses the conversion data-word on Pin DB0 to Pin
DB11. The DB8/HBEN pin assumes its DB8 function. With the
W/B pin tied to logic low, the AD7938-6 interface operates in
byte mode. In this case, the DB8/HBEN pin assumes its HBEN
function. Conversion data from the AD7938-6 must be accessed
in two read operations with eight bits of data provided on DB0
to DB7 for each of the read operations. The HBEN pin determines
whether the read operation accesses the high byte or the low
byte of the12-bit word. For a low byte read, DB0 to DB7 provide
the eight LSBs of the 12-bit word. For a high byte read, DB0 to
DB3 provide the four MSBs of the 12-bit word, DB4 to DB6
provide the Channel ID and DB7 is always a 0.
shows
the read cycle timing diagram for a 12-bit transfer. When operating
in word mode, the HBEN input does not exist, and only the first
read operation is required to access data from the device. When
operating in byte mode, the two read cycles shown in
are required to access the full data-word from the device.
The CS and RD signals are gated internally and the level is
triggered active low. In either word mode or byte mode, CS and
RD can be tied together as the timing specifications for t10 and
t11 are 0 ns minimum. This means the bus would be constantly
driven by the AD7938-6.
The data is placed onto the data bus a time, t13, after both CS
and RD go low. The RD rising edge can be used to latch data
out of the device. After a time, t14, the data lines become
three-stated.
Alternatively, CS and RD can be tied permanently low and the
conversion data is valid and placed onto the data bus a time, t9,
before the falling edge of BUSY.
Note that if RD is pulsed during the conversion time this causes
a degradation in linearity performance of approximately 0.25 LSB.
Reading during conversion by way of tying CS and RD low does
not cause any degradation.
t15
t11
t10
t13
t16
t15
t16
t14
t12
t17
LOW BYTE
HIGH BYTE
DB0 TO DB7
HBEN/DB8
RD
CS
04
75
1-
0
05
Figure 36. AD7938-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/B = 0)
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相關代理商/技術參數(shù)
參數(shù)描述
AD7938BSUZ-REEL7 功能描述:IC ADC 12BIT 8CHAN 32TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極
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