參數(shù)資料
型號： AD7934BRUZ-6
廠商： Analog Devices Inc
文件頁數(shù)： 19/32頁
文件大小： 0K
描述： IC ADC 12BIT 4CH 625KSPS 28TSSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 13.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極；2 個偽差分，單極
AD7933/AD7934
Rev. B | Page 26 of 32
POWER MODES OF OPERATION
The AD7933/AD7934 have four different power modes of
operation. These modes are designed to provide flexible power
management options. Different options can be chosen to optimize
the power dissipation/throughput rate ratio for differing applica-
tions. The mode of operation is selected by PM1 and PM0, the
power management bits, in the control register (see Table 9 for
details). When power is first applied to the AD7933/AD7934, an
on-chip, power-on reset circuit ensures the default power-up
condition is normal mode.
Note that, after power-on, track-and-hold is in hold mode, and
the first rising edge of CONVST places the track-and-hold into
track mode.
Normal Mode (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate performance
wherein the user does not have to worry about any power-up
times because the AD7933/AD7934 remain fully powered up at
all times. At power-on reset, this mode is the default setting in
the control register.
Autoshutdown (PM1 = 0; PM0 = 1)
In this mode of operation, the AD7933/AD7934 automatically
enter full shutdown at the end of each conversion, shown at
Point A in Figure 34 and Figure 38. In shutdown mode, all
internal circuitry on the device is powered down. The part
retains information in the control register during shutdown.
The track-and-hold also goes into hold at this point and remains in
hold as long as the device is in shutdown. The AD7933/AD7934
remains in shutdown mode until the next rising edge of CONVST
(see Point B in Figure 34 and Figure 38). In order to keep the
device in shutdown for as long as possible, CONVST should
idle low between conversions, as shown in Figure 38. On this
rising edge, the part begins to power up and the track-and-hold
returns to track mode. The power-up time required is 10 ms
minimum regardless of whether the user is operating with the
internal or external reference. The user should ensure that the
power-up time has elapsed before initiating a conversion.
Autostandby (PM1 = 1; PM0 = 0)
In this mode of operation, the AD7933/AD7934 automatically
enter standby mode at the end of each conversion, shown as
Point A in Figure 34. When this mode is entered, all circuitry
on the AD7933/AD7934 is powered down except for the
reference and reference buffer. The track-and-hold goes into
hold at this point and remains in hold as long as the device is in
standby. The part remains in standby until the next rising edge
of CONVST powers up the device. The power-up time required
depends on whether the internal or external reference is used.
With an external reference, the power-up time required is a
minimum of 600 ns, while using the internal reference, the
power-up time required is a minimum of 7 μs. The user should
ensure this power-up time has elapsed before initiating another
conversion as shown in Figure 38. This rising edge of CONVST
also places the track-and-hold back into track mode.
Full Shutdown Mode (PM1 = 1; PM0 = 1)
When this mode is entered, all circuitry on the AD7933/AD7934
is powered down upon completion of the write operation, that
is, on the rising edge of WR. The track-and-hold enters hold
mode at this point. The part retains the information in the
control register while in shutdown. The AD7933/AD7934
remain in full shutdown mode, with the track-and-hold in hold
mode, until the power management bits (PM1 and PM0) in the
control register are changed. If a write to the control register
occurs while the part is in full shutdown mode, and the power
management bits are changed to PM0 = PM1 = 0 (normal
mode), the part begins to power up on the WR rising edge, and
the track-and-hold returns to track. To ensure the part is fully
powered up before a conversion is initiated, the power-up time
of 10 ms minimum should be allowed before the CONVST
falling edge; otherwise, invalid data is read.
Note that all power-up times quoted apply with a 470 nF
capacitor on the VREFIN pin.
tPOWER-UP
1
14
BUSY
CLKIN
CONVST
A
B
0
37
13-
04
8
Figure 38. Autoshutdown/Autostandby Mode
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