RSOURCE () T H D ( d B) –40 –45 –50 –55 –80" />
參數(shù)資料
型號： AD7934BRUZ-6
廠商： Analog Devices Inc
文件頁數(shù)： 11/32頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 4CH 625KSPS 28TSSOP
標準包裝： 50
位數(shù)： 12
采樣率（每秒）： 625k
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 1
功率耗散（最大）： 13.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極；2 個偽差分，單極
AD7933/AD7934
Rev. B | Page 19 of 32
RSOURCE ()
T
H
D
(
d
B)
–40
–45
–50
–55
–80
–75
–70
–65
–60
–90
–85
10
100
1k
03
71
3-
01
8
FIN = 50kHz
VDD =5V
VDD =3V
Figure 20. THD vs. Source Impedance in Single-Ended Mode
RSOURCE ()
T
H
D
(
d
B)
–60
–80
–75
–70
–65
–100
–85
–90
–95
10
100
1k
03
71
3-
01
9
FIN = 50kHz
VDD =5V
VDD =3V
Figure 21. THD vs. Source Impedance in Fully Differential Mode
Figure 22 shows a graph of the THD vs. the analog input fre-
quency for various supplies, while sampling at 1.5 MHz with an
SCLK of 25.5 MHz. In this case, the source impedance is 10 Ω.
INPUT FREQUENCY (kHz)
T
HD
(
d
B)
–50
–60
–70
–80
–110
–100
–90
–120
0
100
400
200
300
600
500
700
037
13
-02
0
FSAMPLE = 1.5MSPS
RANGE = 0 TO VREF
VDD =3V
SINGLE-ENDED MODE
VDD =5V/3V
DIFFERENTIAL MODE
VDD =5V
SINGLE-ENDED MODE
Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages
ANALOG INPUTS
The AD7933/AD7934 have software selectable analog input
configurations. Users can choose from among the following
configurations: four single-ended inputs, two fully differential
pairs, or two pseudo differential pairs. The analog input
configuration is chosen by setting the MODE0/MODE1 bits in
the internal control register (see Table 10).
Single-Ended Mode
The AD7933/AD7934 can have four single-ended analog input
channels by setting the MODE0 and MODE1 bits in the control
register to 0. In applications where the signal source has a high
impedance, it is recommended to buffer the analog input before
applying it to the ADC. An amplifier suitable for this function is
the AD8021. The analog input range of the AD7933/AD7934
can be programmed to be either 0 V to VREF, or 0 V to 2 × VREF.
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal to make it the correct format for the ADC.
Figure 23 shows a typical connection diagram when operating
the ADC in single-ended mode. This diagram shows a bipolar
signal of amplitude ±1.25 V being preconditioned before it is
applied to the AD7933/AD7934. In cases where the analog
input amplitude is ±2.5 V, the 3R resistor can be replaced with a
resistor of value R. The resultant voltage on the analog input of
the AD7933/AD7934 is a signal ranging from 0 V to 5 V. In this
case, the 2 × VREF mode can be used.
0.47F
+1.25V
VIN
R
3R
0V
–1.25V
+2.5V
0V
VIN0
VIN3
VREFOUT
AD7933/
AD7934*
*ADDITIONAL PINS OMITTED FOR CLARITY.
03
71
3-
03
1
Figure 23. Single-Ended Mode Connection Diagram
Differential Mode
The AD7933/AD7934 can have two differential analog input
pairs by setting the MODE0 and MODE1 bits in the control
register to 0 and 1, respectively.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 24 defines the fully differential analog
input of the AD7933/AD7934.
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