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參數(shù)資料
| 型號： | AD7934BRUZ-6 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4CH 625KSPS 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 625k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，單極；2 個偽差分，單極 |
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AD7933/AD7934
Rev. B | Page 18 of 32
100...000
011...111
1LSB = 2× VREF/4096 (AD7934)
1LSB = 2× VREF/1024 (AD7933)
–VREF +1 LSB
VREF
+VREF –1 LSB
ADC
CO
DE
100...001
100...010
011...110
000...001
000...000
111...111
03
71
3-
0
2
6
Figure 17. AD7933/AD7934 Ideal Transfer Characteristic
with Twos Complement Output Coding and 2 × VREF Range
TYPICAL CONNECTION DIAGRAM
Figure 18 shows a typical connection diagram for the
AD7933/AD7934. The AGND and DGND pins are connected
together at the device for good noise suppression. If the internal
reference is used, the VREFIN/VREFOUT pin is decoupled to AGND
with a 0.47 μF capacitor to avoid noise pickup. Alternatively,
VREFIN/VREFOUT can be connected to an external reference source.
In this case, decouple the reference pin with a 0.1 μF capacitor.
In both cases, the analog input range can either be 0 V to VREF
(RANGE bit = 0) or 0 V to 2 × VREF (RANGE bit = 1). The
analog input configuration can be either four single-ended
inputs, two differential pairs, or two pseudo differential pairs
supply. The voltage applied to the VDRIVE input controls the
voltage of the digital interface. As shown in Figure 18, it is
connected to the same 3 V supply of the microprocessor to
allow a 3 V logic interface (see the Digital Inputs section).
0.1F
10F
3V/5V
SUPPLY
3V
SUPPLY
AD7933/AD7934
0.1F
0.1F EXTERNAL VREF
0.47F INTERNAL VREF
0 TO VREF/
0 TO 2 × VREF
AGND
DGND
W/B
CLKIN
CS
VDRIVE
VIN0
VDD
VREFIN/VREFOUT
VIN3
10F
2.5V
VREF
RD
CONVST
WR
BUSY
DB0
DB11/DB9
0
371
3-
02
7
+
M
IC
R
OC
ON
T
R
O
L
E
R
/
M
IC
R
O
PR
O
C
ES
SO
R
Figure 18. Typical Connection Diagram
ANALOG INPUT STRUCTURE
Figure 19 shows the equivalent circuit of the analog input
structure of the AD7933/AD7934 in differential/pseudo
differential modes. In single-ended mode, VIN is internally
tied to AGND. The four diodes provide ESD protection for the
analog inputs. Ensure that the analog input signals never exceed
the supply rails by more than 300 mV; doing so causes these
diodes to become forward-biased and start conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
The C1 capacitors in Figure 19 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the sampling capacitors of the ADC and
typically have a capacitance of 45 pF.
For ac applications, removing high frequency components from
the analog input signal is recommended by using an RC low-
pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
drive the analog input from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC. This may necessitate the use of an input buffer amplifier.
The choice of the op amp is a function of the particular
application.
R1
C2
VIN+
VDD
C1
D
R1
C2
VIN–
VDD
C1
D
03
71
3-
02
8
Figure 19. Equivalent Analog Input Circuit,
Conversion Phase: Switches Open, Track Phase: Switches Closed
When no amplifier is used to drive the analog input, limit the
source impedance to low values. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD increases as the source impedance increases
graph of the THD vs. source impedance with a 50 kHz input
tone for both VDD = 5 V and 3 V in single-ended mode and fully
differential mode, respectively.
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