參數(shù)資料
型號(hào)： AD7927BRU
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 8CH 200KSPS 20TSSOP
標(biāo)準(zhǔn)包裝： 75
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 7.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極
配用： EVAL-AD7927CBZ-ND - BOARD EVALUATION FOR AD7927
Data Sheet
AD7927
Rev. D | Page 13 of 28
SEQUENCER OPERATION
The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the
sequencer function. Table 9 outlines the four modes of operation of the sequencer.
Table 9. Sequence Selection
SEQ
SHADOW
Sequence Type
0
This configuration means that the sequence function is not used. The analog input channel selected for each
individual conversion is determined by the contents of the channel address bits, ADD0 through ADD2, in each
prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without
the sequencer function being used, where each write to the AD7927 selects the next channel for conversion (see
0
1
This configuration selects the shadow register for programming. The following write operation loads the contents of
the shadow register. This programs the sequence of channels converted on continuously with each successive valid
CS falling edge (see the Shadow Register section, Table 10, and Figure 12). The channels selected need not be
consecutive.
1
0
If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of
the WRITE operation. This allows other bits in the control register to be altered between conversions while in a
sequence, without terminating the cycle.
1
This configuration is used in conjunction with the channel address bits, ADD2 to ADD0, to program continuous
conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by
the channel address bits in the control register (see Figure 13).
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