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參數(shù)資料
| 型號： | AD7927BRU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 8CH 200KSPS 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
| 配用： | EVAL-AD7927CBZ-ND - BOARD EVALUATION FOR AD7927 |
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Data Sheet
AD7927
Rev. D | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
DIN
AGND
REFIN
AVDD
SCLK
VIN6
VIN7
AGND
20
19
18
17
16
15
14
13
12
11
VDRIVE
DOUT
AGND
VIN2
VIN1
VIN0
VIN5
VIN4
VIN3
AGND
AD7927
TOP VIEW
(Not to Scale)
03
08
8-
0
03
CS
Figure 3. 20-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is
also used as the clock source for the AD7927 conversion process.
2
DIN
Data In. Logic input. Data to be written to the AD7927 control register is provided on this input and is clocked
into the register on the falling edge of SCLK (see the Control Register section).
3
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7927 and framing the serial data transfer.
4, 8, 17, 20
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input signals
and any external reference signal should be referred to this AGND voltage. All AGND pins should be
connected together.
5, 6
AVDD
Analog Power Supply Input. The AVDD range for the AD7927 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN
range, AVDD should be from 4.75 V to 5.25 V.
7
REFIN
Reference Input for the AD7927. An external reference must be applied to this input. The voltage range for
the external reference is 2.5 V ±1% for specified performance.
16 to 9
VIN0 to VIN7
Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed into
the on-chip track-and-hold. The analog input channel to be converted is selected by using the address bits
(ADD2 through ADD0) of the control register. ADD2 through ADD0, in conjunction with the SEQ and
SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend
from 0 V to REFIN or 0 V to 2 × REFIN, as selected via the RANGE bit in the control register. Any unused input
channels should be connected to AGND to avoid noise pickup.
18
DOUT
Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7927
consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to,
followed by the 12 bits of conversion data (MSB first). The output coding may be selected as straight binary or
twos complement via the CODING bit in the control register.
19
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of
the AD7927 operates.
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