參數(shù)資料
型號(hào)： AD7922AUJZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC DUAL 12BIT 2CH TSOT-23-8
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 20mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8 薄型，TSOT-23-8
供應(yīng)商設(shè)備封裝： TSOT-23-8
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 2 個(gè)單端，單極
其它名稱： AD7922AUJZ-REEL7DKR
AD7912/AD7922
Rev. 0 | Page 8 of 32
TIMING EXAMPLES
Figure 6 and Figure 7 show some of the timing parameters from
Timing Example 1
As shown in Figure 7, when fSCLK = 18 MHz and the throughput
is 1 MSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 1 s
With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the
requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 126 ns for tQUIET,
satisfying the minimum requirement of 30 ns.
Timing Example 2
The AD7922 can also operate with slower clock frequencies. As
shown in Figure 7, when fSCLK = 5 MHz and the throughput rate
is 315 kSPS, the cycle time is
t2 + 12.5(1/fSCLK) + tACQ = 3.17 s
With t2 = 10 ns minimum, then tACQ is 664 ns, which satisfies the
requirement of 290 ns for tACQ.
In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where
t10 = 30 ns maximum. This allows a value of 134 ns for tQUIET,
satisfying the minimum requirement of 30 ns.
In this example, as with other slower clock values, the signal
might already be acquired before the conversion is complete,
but it is still necessary to leave 30 ns minimum tQUIET between
conversions. In this example, the signal should be fully acquired
at approximately point C in Figure 7.
04351-0-006
ZERO
X
12
34
5
13
14
15
16
X
CHN
STY
X
CHN
MOD
DB11
DB10
DB2
DB1
DB0
Z
t2
t6
t4
t8
t9
t3
t7
t5
t10
t1
tQUIET
tCONVERT
SCLK
CS
DOUT
THREE-STATE
DIN
B
Figure 6. AD7922 Serial Interface Timing Diagram
04351-0-007
12
3
45
13
14
15
16
tQUIET
tACQUISITION
1/THROUGHPUT
12.5(1/fSCLK)
tCONVERT
BC
SCLK
CS
t10
t2
Figure 7. Serial Interface Timing Example
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