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參數(shù)資料
| 型號： | AD7922AUJZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 12BIT 2CH TSOT-23-8 |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 20mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應商設備封裝： | TSOT-23-8 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
| 其它名稱： | AD7922AUJZ-REEL7DKR |
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AD7912/AD7922
Rev. 0 | Page 23 of 32
04351-0-031
SCLK
CS
DOUT
DON'T CARE
VALID DATA ADC2
VALID DATA ADC1
DON'T CARE
NORMAL MODE
CONVERSION ON THE
TWO DEVICES
NORMAL MODE
CONVERSION ON THE
TWO DEVICES
CHANGE MODE
CS HIGH
BETWEEN THE
10TH–12TH SCLK
FALLING EDGE
DAISY-CHAIN MODE
DATA IS SHIFTED
FROM ONE ADC TO
THE NEXT ONE
DAISY-CHAIN MODE
DATA IS SHIFTED
FROM ONE ADC TO
THE NEXT ONE
DIN
DON'T CARE
CH
≠ STY
CH
≠ STY
DON'T CARE
THE DATA WILL BE
EVENTUALLY LOST,
COMMAND3
SET CHANNEL
FOR ADC2,
COMMAND2
SET CHANNEL
FOR ADC1,
COMMAND1
CHANGE MODE
CS HIGH BETWEEN THE
10TH–13TH SCLK
FALLING EDGE
KEEP THE DEVICES IN
DAISY-CHAIN MODE
Figure 34. Daisy-Chain Diagrams—1
04351-0-032
NORMAL CONVERSION
DAISY-CHAIN CYCLE
THE PARTS ENTER
DAISY-CHAIN MODE
1
16
1
10
1
10
12
14
16
SCLK
CS
DIN
DOUT
DOUT1
(DIN2)*
12
DON'T CARE
COMMAND3 WITH CHN
≠ STY
0, 0, CHN = MOD, VALID DATA ADC1
(0, 0, CHN = STY, VALID DATA ADC1)
DON'T CARE
0, 0, CHN
≠ MOD, VALID DATA ADC1
(0, 0, CHN
≠ STY, VALID DATA ADC1)
0, 0, CHN = MOD, VALID DATA ADC2
DON'T CARE
0, 0, CHN
≠ MOD, VALID DATA ADC2
NOTE
*INFORMATION IN BRACKETS CORRESPONDS TO DATA CLOCKED INTO DIN2 PIN
SCLK
CS
DIN
DOUT
DOUT1
(DIN2)*
COMMAND2 WITH CHN
≠ STY
COMMAND1
DON'T CARE
COMMAND3
COMMAND2
0, 0, CHN = MOD, VALID DATA ADC1
(0, 0, CHN = STY, VALID DATA ADC1)
0, 0, CHN
≠ MOD, VALID DATA ADC1
COMMAND3
0, 0, CHN = MOD, VALID DATA ADC2
DAISY-CHAIN CYCLE
NORMAL CONVERSION
THE PARTS ENTER
NORMAL MODE
1
10
121416
1
10
13
1
16
SHIFTED INTO THE ADC1 INTERNAL REGISTER,
THIS DATA WILL BE EVENTUALLY LOST
SHIFTED INTO THE ADC2
INTERNAL REGISTER
SHIFTED INTO THE ADC1
INTERNAL REGISTER
SHIFTED INTO THE ADC1 INTERNAL REGISTER, IT
CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC1
SHIFTED INTO THE ADC2
INTERNAL REGISTER
SHIFTED INTO THE ADC2 INTERNAL REGISTER, IT
CONTAINS CHANNEL FOR NEXT CONVERSION ON ADC2
Figure 35. Daisy-Chain Diagrams—II
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