參數(shù)資料
型號: AD7922AUJZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 14/32頁
文件大小: 0K
描述: IC ADC DUAL 12BIT 2CH TSOT-23-8
標準包裝: 1
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 20mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8 薄型,TSOT-23-8
供應(yīng)商設(shè)備封裝: TSOT-23-8
包裝: 標準包裝
輸入數(shù)目和類型: 2 個單端,單極
其它名稱: AD7922AUJZ-REEL7DKR
AD7912/AD7922
Rev. 0 | Page 21 of 32
04351-0-028
CS
1
10
12
14
16
1
10
12
14
16
SCLK
DIN
DOUT
CH = STY
CHANNEL FOR NEXT CONVERSION
DAISY-CHAIN CYCLE
NORMAL MODE
VALID DATA
CONVERSION RESULT
Figure 30. Exiting Daisy-Chain Mode with CH = STY in the DIN Pin
04351-0-027
110
13
THE PART ENTERS
NORMAL MODE
A
16
1
16
SCLK
CS
DIN
CHANNEL FOR NEXT CONVERSION
DOUT
INVALID DATA
CONVERSION RESULT
Figure 31. Exiting Daisy-Chain Mode
04351-0-029
CONVERSION CYCLE
DIN: CHN
STY
DAISY-CHAIN MODE
DOUT:CHN
MOD
NORMAL MODE
DOUT: CHN = MOD
CONVERSION CYCLE
DIN: CHN = STY
CONVERSION
CYCLE
*CS HIGH BETWEEN
THE 10TH–12TH SCLK
CS HIGH BETWEEN
THE 2ND–10TH SCLK
CS HIGH BETWEEN
THE 10TH–13TH SCLK
POWER-UP TIME AND CS
HIGH AFTER THE 13TH SCLK
POWER-DOWN
MODE
POWER-UP TIME AND
CS HIGH BETWEEN
THE 10TH–12TH SCLK
CS HIGH BETWEEN
THE 2ND–10TH SCLK
*IF CS IS BROUGHT HIGH BETWEEN THE 10TH AND THE 12TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE
ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS VALID DATA.
IF CS IS BROUGHT HIGH BETWEEN THE 12TH AND THE 13TH SCLK FALLING EDGE, THE DATA SHIFTED FROM ONE
ADC TO THE NEXT ONE IN THE CHAIN, WHILE THE PARTS ARE IN DAISY-CHAIN MODE, IS INVALID DATA.
Figure 32. Transitions between Modes of Operation
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