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參數(shù)資料
| 型號： | AD7836ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT QUAD LC2MOS 44MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 460mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
AD7836
–9–
REV. A
Power-On with CLR Low
The output stage of the AD7836 has been designed to allow
output stability during power-on. If CLR is kept low during
power-on, then just after power is applied to the AD7836, the
situation is as depicted in Figure 14. G1, G4 and G6 are open
while G2, G3 and G5 are closed.
DAC
G1
G3
VOUT
6k
G6
G4
G5
G2
DUTGND
R
Figure 14. Output Stage with VDD < 10 V
VOUT is kept within a few hundred millivolts of DUTGND via
G5 and a 6k
resistor. This thin-film resistor is connected in
parallel with the gain resistors of the output amplifier. The out-
put amplifier is connected as a unity gain buffer via G3, and the
DUTGND voltage is applied to the buffer input via G2. The
amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 14 until
the voltage at VDD and VSS reaches approximately
±10 V. By
now the output amplifier has enough headroom to handle sig-
nals at its input and has also had time to settle. The internal
power-on circuitry opens G3 and G5 and closes G4 and G6. This
situation is shown in Figure 15. Now the output amplifier is
configured in its noise gain configuration via G4 and G6. The
DUTGND voltage is still connected to the noninverting input
via G2 and this voltage appears at VOUT.
DAC
G1
G3
VOUT
6k
G6
G4
G5
G2
DUTGND
R
Figure 15. Output Stage with VDD > 10 V and CLR Low
VOUT has been disconnected from the DUTGND pin by the
opening of G5 but will track the voltage present at DUTGND
via the configuration shown in Figure 15.
When CLR is taken back high, the output stage is configured as
shown in Figure 16. The internal control logic closes G1 and
opens G2. The output amplifier is connected in a noninverting
gain of two configuration. The voltage that appears on the Vout
pins is determined by the data present in the DAC registers. To
set all output voltages to the same known state, a write to
DATA REG E with the SEL pin high allows all DAC registers
to be updated with the same data.
DAC
G1
G3
VOUT
6k
G6
G4
G5
G2
DUTGND
R
Figure 16. Output Stage After CLR Is Taken High
Power-On with CLR High
If CLR is high on the application of power to the device, the
output stages of the AD7836 are configured as in Figure 17
while VDD/VSS are less than
±10 V. G1 is closed and G2 is open
thereby connecting the output of the DAC to the input of its
output amplifier. G3 and G5 are closed while G4 and G6 are
open thus connecting the output amplifier as a unity gain
buffer. VOUT is connected to DUTGND via G5 through a 6 k
resistor until VDD and VSS reach approximately
±10 V.
DAC
G1
G3
VOUT
6k
G6
G4
G5
G2
DUTGND
R
Figure 17. Output Stage Powering Up with CLR High
While VDD/VSS <
±10 V
When the supplies reach
±10 V, the internal power on circuitry
opens G3 and G5 and closes G4 and G6 configuring the output
stage as shown in Figure 18.
DAC
G1
G3
VOUT
6k
G6
G4
G5
G2
DUTGND
R
Figure 18. Output Stage Powering Up with CLR High
When VDD/VSS >
±10 V
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