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參數(shù)資料
| 型號： | AD7836ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT QUAD LC2MOS 44MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 460mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
AD7836
–8–
REV. A
Unipolar Configuration
Figure 11 shows the AD7836 in the unipolar binary circuit con-
figuration. The VREF(+) input of the DAC is driven by the
AD586, a +5 V reference. VREF(–) is tied to ground. Table II
gives the code table for unipolar operation of the AD7836.
Other suitable references include the REF02, a precision 5 V
reference, and the REF195, a low dropout, micropower preci-
sion +5 V reference.
*ADDITIONAL PINS OMITTED FOR CLARITY
+15V
+5V
VOUT
(0 TO +10V)
VCC
2
6
8
5
4
SIGNAL
GND
C1
1nF
AGND
DGND
VDD
VOUT
VREF(+)
VREF(–)
VSS
–15V
R1
10k
AD7836
*
AD586
SIGNAL
GND
DUTGND
Figure 11. Unipolar +5 V Operation
Offset and gain may be adjusted in Figure 2 as follows: To ad-
just offset, disconnect the VREF(–) input from 0 V, load the DAC
with all 0s and adjust the VREF(–) voltage until VOUT = 0 V. For
gain adjustment, the AD7836 should be loaded with all 1s and
R1 adjusted until VOUT = 10 V(16383/16384) = 9.999389.
Many circuits will not require these offset and gain adjustments. In
these circuits R1 can be omitted. Pin 5 of the AD586 may be left
open circuit and Pin 2 (VREF(–)) of the AD7836 tied to 0 V.
Table II. Code Table for Unipolar Operation
Binary Number in DAC Latch
Analog Output
MSB
LSB
(VOUT)
11
1111
2 VREF (16383/16384) V
10
0000
2 VREF (8192/16384) V
01
1111
2 VREF (8191/16384) V
00
0000
0001
2 VREF (1/16384) V
00
0000
0 V
NOTE
VREF = VREF(+); VREF(–) = 0 V for unipolar operation.
For VREF(+) = +5 V, 1 LSB = +10 V/2
14 = +10 V/16384 = 610
V.
Bipolar Configuration
Figure 12 shows the AD7836 set up for
±10 V operation. The
AD588 provides precision
±5 V tracking outputs that are fed to
the VREF(+) and VREF(–) inputs of the AD7836. The code table
for bipolar operation of the AD7836 is shown in Table III.
In Figure 12, full-scale and bipolar zero adjustments are pro-
vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the
+5 V and –5 V outputs together with respect to ground.
For bipolar-zero adjustment, the DAC is loaded with
1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale
is adjusted by loading the DAC with all 1s and adjusting R2 un-
til VOUT = 10(8191/8192) V = 9.998779 V.
When bipolar-zero and full-scale adjustment are not needed,
R2 and R3 can be omitted. Pin 12 on the AD588 should be
connected to Pin 11 and Pin 5 should be left floating.
*ADDITIONAL PINS OMITTED FOR CLARITY
+15V
+5V
VOUT
(–10V TO +10V)
VCC
AGND
DGND
VDD
VOUT
VREF(+)
VREF(–)
VSS
–15V
AD7836
*
SIGNAL
GND
DUTGND
6
3
4
C1
1 F
R2
100k
2
14
15
16
12 8 13
11
10
5
9
7
R3
100k
R1
39k
1
AD588
Figure 12. Bipolar
±5 V Operation
Table III. Code Table for Bipolar Operation
Binary Number in DAC Latch
Analog Output
MSB
LSB
(VOUT)
11
1111
2[VREF(–) + VREF (16383/16384)] V
10
0000
0001
2[VREF(–) + VREF (8193/16384)] V
10
0000
2[VREF(–) + VREF (8192/16384)] V
01
1111
2[VREF(–) + VREF (8191/16384)] V
00
0000
0001
2[VREF(–) + VREF (1/16384)] V
00
0000
2[VREF(–)] V
NOTE
VREF = (VREF(+) – VREF(–)).
For VREF(+) = +5 V, and VREF(–) = –5 V, VREF =10 V, 1 LSB = 2 VREF V/2
14
= 20 V/16384 = 1220
V.
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7836 is shown in
Figure 13. It is capable of driving a load of 5 k
in parallel
with 50 pF. G1 to G6 are transmission gates that are used to
control the power on voltage present at VOUT. On power up G1
and G2 are also used in conjunction with the CLR input to set
VOUT to the user defined voltage present at the DUTGND pin.
When CLR is taken back high the DAC outputs reflect the data
in the DAC registers.
DAC
G1
G3
VOUT
6k
G6
G4
G5
G2
DUTGND
R = 13.5k
R
Figure 13. Block Diagram of AD7836 Output Stage
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