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參數(shù)資料
| 型號： | AD7834AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SOT-23 -40 to 125 |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PDSO28 |
| 封裝： | MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 404K |
| 代理商： | AD7834AR |
REV. A
–12–
AD7834/AD7835
The V
REF
pins should never be allowed to float when power is
applied to the part. (V
REF
(+) should never be allowed to go
below V
REF
(–)–0.3 V. V
REF
(–) should never be allowed to go
below V
SS
–0.3 V. V
DD
should never be allowed to go below
V
CC
–0.3 V.
In some systems it may be necessary to introduce one or more
Schottky diodes between pins to prevent the above situations
arising at power-on. These diodes are shown in Figure 19. How-
ever in most systems, with careful consideration given to power
supply sequencing, the above rules will be adhered to and pro-
tection diodes won’t be necessary.
V
REF
(+)
V
REF
(–)
AD7834
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
SD103C
1N5711
1N5712
Figure 19. Power-ON Protection
MICROPROCESSOR INTERFACING
AD7834 to 80C51 Interface
A serial interface between the AD7834 and the 80C51 micro-
controller is shown in Figure 20. TXD of the 80C51 drives
SCLK of the AD7834 while RXD drives the serial data line of
the part.
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. The AD7834 expects the MSB of the
24-bit write first. Therefore, the user will have to ensure that
the data in the SBUF register is arranged correctly so that this is
taken into account. When data is to be transmitted to the part,
P3.3 is taken low. Data on RXD is valid on the falling edge of
TXD. The 80C51 transmits its data in 8-bit bytes with only 8
falling clock edges occurring in the transmit cycle. To load data
to the AD7834, P3.3 is left low after the first eight bits are
transferred. A second byte is then transferred, with P3.3 still
kept low. After the third byte has been transferred, the P3.3
line is taken high.
CLR
LDAC
FSYNC
SCLK
DIN
P3.5
P3.4
P3.3
TXD
RXD
*
ADDITIONAL PINS OMITTED FOR CLARITY
AD7834
*
80C51
*
Figure 20. AD7834 to 80C51 Interface
LDAC
and
CLR
on the AD7834 are also controlled by 80C51
port outputs. The user can bring
LDAC
low after every three
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in-
put registers have been loaded (twelve byte transmits) and then
update the DAC outputs.
AD7834 to 68HC11 Interface
Figure 21 shows a serial interface between the AD7834 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7834 while the MOSI output drives the serial data line,
DIN, of the AD7834. The FSYNC signal is derived from port
line PC7 in this example.
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transferred to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes, MSB first. The AD7834 expects the MSB
of the 24-bit write first also. Eight falling clock edges occur in
the transmit cycle. To load data to the AD7834, PC7 is left low
after the first eight bits are transferred. A second byte of data is
then transmitted serially to the AD7834. Then a third byte is
transmitted, and when this transfer is complete, the PC7 line is
taken high.
CLR
LDAC
FSYNC
SCLK
DIN
PC5
PC6
PC7
SCK
MOSI
*
ADDITIONAL PINS OMITTED FOR CLARITY
AD7834
*
68HC11
*
Figure 21. AD7834 to 68HC11 Interface
In Figure 21,
LDAC
and
CLR
are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7834 can be updated after each three-byte transfer, or else
all DACs can be simultaneously updated after twelve bytes have
been transferred.
AD7834 to ADSP-2101 Interface
An interface between the AD7834 and the ADSP-2101 is shown
in Figure 22. In the interface shown, SPORT0 is used to trans-
fer data to the part. SPORT1 is configured for alternate func-
tions. FO, the flag output on SPORT1, is connected to
LDAC
and is used to load the DAC latches. In this way data can be
transferred from the ADSP-2101 to all the input registers in the
DAC and the DAC latches can be updated simultaneously. In
the application shown, the
CLR
pin on the AD7834 is con-
trolled by circuitry that monitors the power in the system.
CLR
LDAC
FSYNC
SCLK
DIN
FO
TFS
SCK
DT
*
ADDITIONAL PINS OMITTED FOR CLARITY
AD7834
*
ADSP-2101
*
POWER
MONITOR
Figure 22. AD7834 to ADSP-2101 Interface
The AD7834 requires 24 bits of serial data framed by a single
FSYNC
pulse. It is necessary that this
FSYNC
pulse stays low
until all the data has been transferred. This can be provided by
the ADSP-2101 in one of two ways. Both require setting the se-
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