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| 型號： | AD7834SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | LC2MOS Quad 14-Bit DAC |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 14-BIT DAC, CDIP28 |
| 封裝： | 0.600 INCH, CERDIP-28 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 404K |
| 代理商： | AD7834SQ |
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
LC
2
MOS
Quad 14-Bit DAC
AD7834/AD7835
Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Four 14-Bit DACs in One Package
AD7834—Serial Loading
AD7835—Parallel 8-/14-Bit Loading
Voltage Outputs
Power-On Reset Function
Max/Min Output Voltage Range of +/–8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface Mount Packages
AD7834—28-Pin SO, DIP and Cerdip
AD7835—44-Pin PQFP and PLCC
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output volt-
ages in the range of
±
8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
0s, into one of the input latches via DIN, SCLK and
FSYNC
.
The AD7834 has five dedicated package address pins, PA0–
PA4, that can be wired to AGND or V
CC
to permit up to 32
AD7834s to be individually addressed in a multipackage
application.
The AD7835 can accept either 14-bit parallel loading or
double-byte loading, where right-justified data is loaded in one
8-bit and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the
WR
,
CS
,
BYSHF
and DAC channel address pins, A0–A2.
With either device, the
LDAC
signal can be used to update
either all four DAC outputs simultaneously or individually,
on reception of new data. In addition, for either device, the
asynchronous
CLR
input can be used to set all signal outputs,
V
OUT
1–V
OUT
4, to the user-defined voltage level on the Device
Sense Ground pin, DSG. On power-on, before the power sup-
plies have stabilized, internal circuitry holds the DAC output
voltage levels to within
±
2 V of the DSG potential. As the sup-
plies stabilize, the DAC output levels move to the exact DSG
potential (assuming
CLR
is exercised).
The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP pack-
ages, and the AD7835 is available in a 44-pin PQFP package
and a 44-pin PLCC package.
AD7835 FUNCTIONAL BLOCK DIAGRAM
X1
DAC 1
RIN1
V
CC
V
DD
V
SS
V
REF
(–)A V
REF
(+)A
V
OUT
1
BYSHF
DB13
DB0
A0
A1
A2
CS
X1
DAC 2
DAC 2
INPUT
REG2
X1
DAC 3
INPUT
REG3
X1
DAC 4
RIN4
DAC 1
AD7835
V
OUT
2
V
OUT
3
V
OUT
4
AGND
DGND
LDAC
DSG B
CLR
DSG A
DAC 4
DAC 3
V
REF
(–)B V
REF
(+)B
DECODE
INPUT
WR
14
AD7834 FUNCTIONAL BLOCK DIAGRAM
X1
DAC 1
INPUT
REG1
V
CC
V
DD
V
SS
V
REF
(–) V
REF
(+)
V
OUT
1
PAEN
PA0
PA1
PA2
PA3
PA4
CLOGIC
&
DECODE
PARALLEL
CONVERTER
FSYNC
DIN
SCLK
X1
DAC 2
DAC 2
INPUT
REGISTER
2
X1
DAC 3
DAC 3
RINPUT
3
X1
DAC 4
LATCH
DAC 4
RIN4
DAC 1
AD7834
V
OUT
2
V
OUT
3
V
OUT
4
AGND
DGND
LDAC
DSG
CLR
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