參數(shù)資料
型號： AD7834AR
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 2.35V-5.25V, 12 bit, 1MSPS, Serial ADC 6-SOT-23 -40 to 125
中文描述： QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PDSO28
封裝： MS-013AE, SOIC-28
文件頁數(shù)： 10/16頁
文件大小： 404K
代理商： AD7834AR
REV. A
–10–
AD7834/AD7835
Table IV. Code Table for Unipolar Operation
Binary Number in DAC Latch
MSB
Analog Output
(V
OUT
)
LSB
11
10
01
00
00
1111
0000
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
V
REF
(16383/16384) V
V
REF
(8192/16384) V
V
REF
(8191/16384) V
V
REF
(1/16384) V
0 V
NOTE
V
= V
(+); V
(–) = 0 V for unipolar operation.
For V
REF
(+) = +5 V, 1 LSB = +5 V/2
14
= +5 V/16384 = 305
μ
V.
Bipolar Configuration
Figure 14 shows the AD7834/AD7835 set up for
±
5 V opera-
tion. The AD588 provides precision
±
5 V tracking outputs
which are fed to the V
REF
(+) and V
REF
(–) inputs of the AD7834/
AD7835. The code table for bipolar operation of the AD7834/
AD7835 is shown in Table V.
+15V
+5V
V
(–5 TO +5V)
V
CC
6
3
4
C1
1μF
AGND
DGND
V
DD
V
OUT
V
REF
(+)
V
REF
(–)
V
SS
–15V
*
ADDITIONAL PINS OMITTED FOR CLARITY
R2
100k
AD7834/
AD7835
*
SIGNAL
GND
2
14
15
16
12
8
13
11
10
5
9
7
R3
100k
R1
1
AD588
Figure 14. Bipolar
±
5 V Operation
Table V. Code Table for Bipolar Operation
Binary Number in DAC Latch Analog Output
MSB
LSB
(V
OUT
)
11
10
10
01
00
00
1111
0000
0000
1111
0000
0000
1111
0000
0000
1111
0000
0000
1111
0001
0000
1111
0001
0000
V
REF
(–) + V
REF
(16383/16384) V
V
REF
(–) + V
REF
(8193/16384) V
V
REF
(–) + V
REF
(8192/16384) V
V
REF
(–) + V
REF
(8191/16384) V
V
REF
(–) + V
REF
(1/16384) V
V
REF
(–) V
NOTE
V
REF
= (V
REF
(+) – V
REF
(–)).
For V
REF
(+) = +5 V, and V
REF
(–) = –5 V, 1 LSB = 10 V/2
14
= 10 V/16384 =
610
μ
V.
In Figure 14, full-scale and bipolar zero adjustments are pro-
vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the
+5 V and –5 V outputs together with respect to ground.
For bipolar-zero adjustment, the DAC is loaded with
1000 . . . 0000 and R3 is adjusted until V
OUT
= 0 V. Full scale
is adjusted by loading the DAC with all 1s and adjusting R2 un-
til V
OUT
= 5(8191/8192) V = 4.99939 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted. Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
When 14-bit transfers are being used, the DAC output voltages,
V
OUT
1–V
OUT
4, can be updated to reflect new data in the DAC
input registers in one of two ways. The first method normally
keeps
LDAC
high and only pulses
LDAC
low momentarily to
update all DAC latches simultaneously with the contents of
their respective input registers. The second method ties
LDAC
low and channel updating occurs on a per channel basis after
new data is loaded to an input register.
In order to avoid the DAC output going to an intermediate
value during a 2-byte transfer,
LDAC
should not be tied low
permanently, but should be held high until the 2 bytes are writ-
ten to the input register. When the selected input register has
been loaded with the 2 bytes,
LDAC
should then be pulsed low
to update the DAC latch and, hence, perform the digital-to-
analog conversion.
In many applications, it may be acceptable to allow the DAC
output to go to an intermediate value during a 2-byte transfer.
In such applications,
LDAC
can be tied low, thus using one less
control line.
The actual DAC input register that is being written to is deter-
mined by the logic levels present on the devices address lines, as
shown in Table III.
Table III. AD7835—Address Line Truth Table
A2
A1
A0
DAC Selected
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
DAC 1
DAC 2
DAC 3
DAC 4
All DACs Selected
Unipolar Configuration
Figure 13 shows the AD7834/AD7835 in the unipolar binary
circuit configuration. The V
REF
(+) input of the DAC is driven
by the AD586, a +5 V reference. V
REF
(–) is tied to ground.
Table IV gives the code table for unipolar operation of the
AD7834/AD7835.
+15V
+5V
V
(0 TO +5V)
V
CC
2
6
8
5
4
SIGNAL
GND
C1
1nF
AGND
DGND
V
DD
V
OUT
V
REF
(+)
V
REF
(–)
V
SS
–15V
*
ADDITIONAL PINS OMITTED FOR CLARITY
R1
10k
AD7834/
AD7835
*
AD586
SIGNAL
GND
Figure 13. Unipolar +5 V Operation
Offset and gain may be adjusted in Figure 13 as follows: To ad-
just offset, disconnect the V
REF
(–) input from 0 V, load the DAC
with all 0s and adjust the V
REF
(–) voltage until V
OUT
= 0 V. For
gain adjustment, the AD7834/AD7835 should be loaded with
all 1s and R1 adjusted until V
OUT
= 5 V(16383/16384) =
4.999695.
Many circuits will not require these offset and gain adjustments. In
these circuits R1 can be omitted. Pin 5 of the AD586 may be left
open circuit and Pin 2 (V
REF
(–)) of the AD7834/AD7835 tied to
0 V.
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