參數(shù)資料
型號: AD7824
廠商: Analog Devices, Inc.
英文描述: High Speed 4-Channel 8-Bit ADC(四通道LC2MOS高速8位A/D轉(zhuǎn)換器)
中文描述: 高速4通道8位ADC(四通道LC2MOS高速8位的A / D轉(zhuǎn)換器)
文件頁數(shù): 8/12頁
文件大小: 273K
代理商: AD7824
AD7824/AD7828
REV. C
–8–
UNIPOLAR OPE RAT ION
T he analog input range for any channel of the AD7824/ AD7828
is 0 V to 5 V as shown in the unipolar operational diagram of Fig-
ure 10. Figure 11 shows the designed code transitions which
occur midway between successive integer L SB values (i.e.,
1/2 LSB, 3/2 LSB, 5/2 LSB, FS 3/2 LSBs). T he output code is
Natural Binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.
Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation
Figure 11. Ideal Input/Output Transfer Characteristic for
Unipolar 0 V to +5 V Operation
BIPOLAR OPE RAT ION
T he circuit of Figure 12 is designed for bipolar operation. An
AD544 op-amp conditions the signal input (V
IN
) so that only
positive voltages appear at AIN 1. T he closed loop transfer
function of the op amp for the resistor values shown is given
below:
AIN
1 = (2.5 – 0.625
)
Volts
T he analog input range is
±
4 V and the LSB size is 31.25 mV.
T he output code is complementary offset binary. T he ideal
input/output characteristic is shown in Figure 13.
Figure 12. AD7824/AD7828 Bipolar
±
4 V Operation
Figure 13. Ideal Input/Output Transfer Characteristic for
±
4 V Operation
T IMING AND CONT ROL
T he AD7824/AD7828 has two digital inputs for timing and
control. T hese are Chip Select (
CS
) and Read (
RD
). A READ
operation brings
CS
and
RD
low which starts a conversion on
the channel selected by the multiplexer address inputs (see
T able I). T here are two modes of operation as outlined by the
timing diagrams of Figures 14 and 15. Mode 0 is designed for
microprocessors which can be driven into a WAIT state. A
READ operation (i.e.,
CS
and
RD
are taken low) starts a con-
version and data is read when conversion is complete. Mode l
does not require microprocessor WAIT states. A READ opera-
tion initiates a conversion and reads the previous conversion
results.
T able I. T ruth T able for Input Channel Selection
AD7824
A1
AD7828
A1
A0
A2
A0
Channel
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN 1
AIN 2
AIN 3
AIN 4
AIN 5
AIN 6
AIN 7
AIN 8
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