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參數(shù)資料
| 型號： | AD7799 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, 24-Bit/16-Bit Sigma-Delta ADC with In-Amp |
| 中文描述： | 低功耗，24-Bit/16-BitΣ-Δ型ADC在放大器 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 499K |
| 代理商： | AD7799 |
Preliminary Technical Data
AD7798/AD7799
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REV. PrD. Page 9 of 17
3
4
5
14
13
12
DVDD
AVDD
GND
1
2
16
15
DIN
DOUT/RDY
6
7
8
11
10
9
PWRSW
AD7799/98
TOP VIEW
(Not To Scale)
REFIN(-)
REFIN(+)
AIN3(+)/P1
AIN3(-)/P2
AIN1(+)
SCLK
CS
AIN1(-)
AIN2(+)
AIN2(-)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
Mnemonic
1
SCLK
Function
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making
the interface suitable for opto-isolated applications. The serial clock can be continuous with all data
transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to or from the ADC in smaller batches of data.
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC
in systems with more than one device on the serial bus or as a frame synchronization signal in communi-
cating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK,
DIN, and DOUT used to interface with the device.
Analog Input/Digital Output pin. AIN3(+) is the positive terminal of the differential analog input pair
AIN3(+)/AIN3(-). Alternatively, this pin can function as a general purpose output bit referenced between
AV
DD
and GND
Analog Input/ Digital Output pin. AIN3(–) is the negative terminal of the differential analog input pair
AIN3(+)/AIN3(-). Alternatively, this pin can function as a general purpose output bit referenced between
AV
DD
and GND
Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(-).
Analog Input. AIN1(–) is the negative terminal of the differential analog input pair AIN1(+)/AIN1(-).
Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(-).
Analog Input. AIN2(–) is the negative terminal of the differential analog input pair AIN2(+)/AIN2(-).
Positive Reference Input. REFIN(+) can lie anywhere between AV
DD
and GND + 0.1 V.
The nominal reference voltage (REFIN(+) – REFIN(–)) is 2.5 V, but the part functions with a reference from 0.1
V to AV
.
Negative Reference Input. This reference input can lie anywhere between GND and AV
DD
– 0.1 V.
Low Side Power Switch to GND.
Ground Reference Point.
Supply Voltage, 2.7 V to 5.25 V.
Serial Interface Supply voltage, 2.7 V to 5 V. DV
DD
is independent of AV
DD
, therefore the serial interface can
be operated at 3V with V
DD
at 5V or vice versa.
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose . It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin,
going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will
go high before the next update occurs.
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.
With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control
word informa-tion is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising
edge.
The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the
DOUT/RDY pin is three-stated but the RDY bit remains active.
2
CS
3
AIN3(+)/P1
4
AIN3(–)/P2
5
6
7
8
9
AIN1(+)
AIN1(-)
AIN2(+)
AIN2(-)
REFIN(+)
10
11
12
13
14
REFIN(-)
PSW
GND
AV
DD
DV
DD
15
DOUT/RDY
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