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參數(shù)資料
| 型號(hào)： | AD7799 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, 24-Bit/16-Bit Sigma-Delta ADC with In-Amp |
| 中文描述： | 低功耗，24-Bit/16-BitΣ-Δ型ADC在放大器 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 499K |
| 代理商： | AD7799 |
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Preliminary Technical Data
AD7798/AD7799
STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; POWER-ON/RESET = 0x88)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load bits RS2, RS1 and RS0 with 0. Table 7 outlines the bit designations for the status register.
SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.
REV. PrD. Page 13 of 17
SR7
RDY(1)
SR6
ERR(0)
SR5
NOREF(0)
SR4
0(0)
SR3
0/1
SR2
CH2(0)
SR1
CH1(0)
SR0
CH0(0)
Table 7. Status Register Bit Designations
Bit Location
Bit Name
SR7
RDY
Description
Ready bit for ADC.
Cleared
when data is written to the ADC data register. The RDY bit is
set
automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to indicate to the user not to read the conversion data. It is also
set
when the part
is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin
can be used as an alternative to the status register for monitoring the ADC for conversion data.
ADC Error Bit. This bit is written to at the same time as the RDY bit.
Set
to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,
underrange, NOREF
Cleared
by a write operation to start a conversion.
No Reference Bit.
Set
to indicate that one or both of the REFIN pins is floating or the applied voltage is
below a specified threshold. When
set
, conversion results are clamped to all ones.
Cleared
to indicate that a valid reference is applied between REFIN(+) and REFIN(-).
The NOREF bit is enabled by setting the REF_DET bit in the Configuration register to 1. The ERR bit is
also set if the voltage applied to the reference input is invalid.
This bit is automatically
cleared
.
This bit is automatically
cleared
on the AD7798, and is automatically
set
on the AD7799.
These bits indicate which channel is being converted by the ADC.
SR6
ERR
SR5
NOREF
SR4
SR3
SR2–SR0
MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; POWER-ON/RESET = 0x000A)
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure the
Low Side Power Switch, select the mode of the ADC and select the ADC update rate. Table 8 outlines the bit designations for the mode
register. MR0 through MR15 indicate the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the
data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the setup register resets the
modulator and filter and sets the RDY bit.
0
0/1
CH2–CH0
MR15
MD2(0)
MR7
(0)
MR14
MD1(0)
MR6
(0)
MR13
MD0(0)
MR5
0(0)
MR12
PSW(0)
MR4
0(0)
MR11
0(0)
MR3
FS3(1)
MR10
0(0)
MR2
FS2(0)
MR9
0(0)
MR1
FS1(1)
MR8
0(0)
MR0
FS0(0)
Table 8. Mode Register Bit Designations
Bit Location
Bit Name
MR15–MR13
MD2–MD0
MR12
PSW
Description
Mode Select Bits. These bits select the operational mode of the AD7798/AD7799 (See
Table 9).
Power Switch Control Bit.
Set
by user to close the power switch PSW to GND. The power switch can sink up to 20 mA.
Cleared
by user to open the power switch.
When the ADC is placed in power-down mode, the power switch is opened.
These bits must be programmed with a Logic 0 for correct operation.
Filter Update Rate Select Bits (see Table 10).
MR11-MR4
MR3-MR0
0
FS3-FS0
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