AVDD1 = DV
參數(shù)資料
型號(hào): AD7763BSVZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 30/33頁(yè)
文件大小: 0K
描述: IC ADC 24BIT S/D 625KSPS 64-TQFP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 24
采樣率(每秒): 625k
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 955.5mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-TQFP-EP(10x10)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極;1 個(gè)差分,雙極
Data Sheet
AD7763
Rev. B | Page 5 of 32
TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMCLK
1
MHz min
Applied master clock frequency
40
MHz max
fICLK
500
kHz min
Internal modulator clock derived from MCLK
20
MHz max
1 × tICLK or 0.5 × tICLK2
typ
SCO high period
1 × tICLK or 0.5 × tICLK2
typ
SCO low period
t3
tSCO3
typ
DRDY low period
2
ns typ
SCO rising edge to DRDY falling edge
3
ns typ
SCO rising edge to DRDY rising edge
32 × tSCO3
typ
FSO low period
1
ns typ
SCO rising edge to FSO falling edge
2
ns typ
SCO falling edge to FSO rising edge
t5
6.5
ns max
Initial data access time
t64
5
ns max
SCO rising edge to SDO valid
t7
0.5 × tSCO3
ns min
SDO valid after SCO falling edge
t8
16 × tSCO3
typ
DRDY rising edge to SDL falling edge
t9
tSCO3
typ
SDL pulse width
t10
5.5
ns max
SDO three-state to SCO rising edge
t11
1 × tSCO3
min
FSI low period
t12
12
ns min
SDI setup time
t13
10
ns min
SDI hold time
t14
12
ns min
FSI setup time
t15
16 × tSCO3
typ
SDL falling edge to SDL falling edge
1
tICLK = 1/fICLK.
2
SCO frequency selected by SCR and CDIV pins.
3
tSCO = t1 + t2.
4
All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1.
5
In decimate × 32 mode, this time specification applies only when CDIV = 0 and SCR =1. For all other combinations of CDIV and SCR in decimate × 32 mode, the FSO
signal is constantly logic low.
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