參數(shù)資料
型號(hào)： AD7739BRUZ-REEL7
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 8CH SIG-DEL 24TSSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
采樣率（每秒）： 15.1k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 100mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
配用： EVAL-AD7739EBZ-ND - BOARD EVAL FOR AD7739
Data Sheet
AD7739
Rev. A | Page 29 of 32
ADC Full-Scale Self-Calibration
The ADC full-scale self-calibration can reduce the ADC full-
scale error for the +2.5 V and ±2.5 V input range. If repeated
after a temperature change, it can also reduce the full-scale drift.
The ADC full-scale self-calibration is performed with a +2.5 V
input voltage range on internally generated full-scale voltage
(VREF), regardless of the input voltage range set in the channel
setup register. Full-scale errors in the ±1.25 V, +1.25 V, ±0.625 V,
and +0.625 V ranges are not calibrated as this requires an
accurate low voltage source other than the reference.
If the 1.25 V or 0.625 V ranges are used on any channel, the
ADC full-scale self-calibration is not recommended. Perform
a system full-scale calibration if accurate gains need to be
achieved on these ranges.
It is recommended that the ADC full-scale calibration register
be updated only as part of an ADC full-scale self-calibration for
the +2.5 V and ±2.5 V input range.
Per Channel System Calibration
The per channel system calibration can reduce the system offset
error and the system gain error. If repeated after a temperature
change, it can also reduce the system offset and gain drifts.
If the per channel system calibrations are used, initiate these in
the following order: a channel zero-scale system calibration,
followed by a channel full-scale system calibration.
The system calibration is affected by the ADC zero-scale and
full-scale calibration registers. Therefore, if both self-calibration
and system calibration are used in the system, perform an ADC
self-calibration first, followed by a system calibration cycle.
Set the voltage range in the channel setup register before
executing the channel system calibration.
While executing a system calibration, the fully settled system
zero-scale voltage signal or system full-scale voltage signal must
be connected to the selected channel analog inputs.
The per channel calibration registers can be read, stored, or
modified and written back to the AD7739. Note that when
writing the calibration registers, the AD7739 must be in idle
mode. Note that outside the specified calibration range,
calibration is possible, but the performance may degrade
(see the System Calibration section in Table 1).
Figure 27. Typical Connections for the AD7739 Application
0.1
F
+
10
F
ADR421
AVDD
+
10
F
0.1
F
AVDD
CLOCK
GENERATOR
MCLKIN
MCLKOUT
33pF
6.144MHz
DVDD
+
10
F
0.1
F
DVDD
24-BIT
Σ- ADC
BUFFER
AD7739
AIN7
MUX
AINCOM
AIN0
SERIAL
INTERFACE
AND
CONTROL
LOGIC
SCLK
DIN
DOUT
CS
RDY
RESET
REFIN(-)
REFIN(+)
DGND
AGND
HOST
SYSTEM
ANALOG
INPUTS
DVDD
0.1
F
0.1
F
0.1
F
0.1
F
100
100
100
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