參數(shù)資料
型號(hào)： AD7732BRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/32頁(yè)
文件大小： 0K
描述： IC ADC 24BIT 2-CH 28-TSSOP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 15.4k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 100mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極；2 個(gè)差分，雙極
配用： EVAL-AD7732EBZ-ND - BOARD EVAL FOR AD7732
AD7732
Rev. A | Page 17 of 32
ADC Status Register
8 Bits, Read-Only Register, Address 04h, Default Value 00h
In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel
data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to
0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the channel
data register. Writing to the mode register resets all the bits to 0.
In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the
calibration is complete.
The RDY pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register.
The RDY0 bit corresponds to the differential input 0, and the RDY1 bit corresponds to the differential input 1.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mnemonic
–
RDY1
–
RDY0
Default
0
Checksum Register
16 Bits, Read/Write Register, Address 05h
This register is described in the Using the
AD7732/AD7734/AD7738/AD7739 Checksum Register
application note, (www.analog.com/AN-626).
ADC Zero-Scale Calibration Register
24 Bits, Read/Write Register, Address 06h, Default Value 800000h
The register holds the ADC zero-scale calibration coefficient.
The value in this register is used in conjunction with the value
in the ADC full-scale calibration register and the corresponding
channel zero-scale and channel full-scale calibration registers to
scale digitally all channels’ conversion results. The value in this
register is updated automatically following the execution of an
ADC zero-scale self-calibration. Writing this register is
possible in the idle mode only (see the Calibration section for
more details).
ADC Full-Scale Register
24 Bits, Read/Write Register, Address 07h, Default Value 800000h
This register holds the ADC full-scale coefficient. The user is
advised not to change the default configuration of this register.
Channel Data Registers
16 Bit/24 Bit, Read-Only Registers, Address 08h, 0Ah, Default
Width 16 Bits, Default Value 8000h
These registers contain the most up-to-date conversion results
corresponding to each analog input channel. The 16-bit or 24-
bit data width can be configured by setting the 16 bit/24 bit in
the mode register. The relevant RDY bit in the channel status
register goes high when the result is updated. The RDY bit will
return low once the data register reading has begun. The RDY
pin can be configured to indicate when any channel has unread
data or waits until all enabled channels have unread data. If any
channel data register read operation is in progress when a new
result is updated, no update of the data register will occur. This
avoids having corrupted data. Reading the status registers can
be associated with reading the data registers in the dump mode.
Reading the status registers is always associated with reading
the data registers in the continuous read mode (see the Digital
Interface Description section for more details).
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