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參數(shù)資料
| 型號： | AD7732 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, +-10 V Input Range, High Throughput, 24-Bit SIGMA- ADC |
| 中文描述： | 2通道，-10 V輸入范圍，高通量，24位Σ-模數(shù)轉換器 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大小： | 1576K |
| 代理商： | AD7732 |
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AD7732
Analog Input’s Extended Voltage Range
Rev. 0 | Page 27 of 32
The AD7732 output data code span corresponds to the nominal
input voltage range. The ADC is functional outside the nominal
input voltage range, but the performance might degrade. The
sigma-delta modulator was designed to fully cover a ±11.6 V
differential input voltage; outside this range, the performance
might degrade more rapidly. The adjacent channels are not
affected by up to ±16.5 V absolute analog input voltage
(Figure 8).
When the CLAMP bit in the mode register is set to 1, the
channel data register will be digitally clamped to either all 0s or
all 1s when the analog input voltage goes outside the nominal
input voltage range.
As shown in Table 16 and Table 17, when CLAMP = 0, the data
reflects the analog input voltage outside the nominal voltage
range. In this case, the SIGN and OVR bits in the channel status
register should be considered along with the data register value
to decode the actual conversion result.
Note that the OVR bit in the channel status register is generated
digitally from the conversion result and indicates the sigma-
delta modulator (nominal) overrange. The OVR bit DOES NOT
indicate exceeding the AIN pin’s absolute voltage limits.
Table 16. Extended Input Voltage Range,
Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0
Input (V)
11.60039
10.00061
10.00031
10.00000
0.00031
0.00000
–0.00031
–10.00000
–10.00031
–10.00061
–11.60040
Data (hex)
147B
0001
0000
FFFF
8001
8000
7FFF
0000
FFFF
FFFE
EB85
SIGN
0
0
0
0
0
0
1
1
1
1
1
OVR
1
1
1
0
0
0
0
0
1
1
1
Table 17. Extended Input Voltage Range, Nominal
Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0
Input (V)
11.60006
10.00031
10.00015
10.00000
0.00015
0.00000
–0.00015
Data (hex)
28F5
0001
0000
FFFF
0001
0000
0000
SIGN
0
0
0
0
0
0
1
OVR
1
1
1
0
0
0
1
Chopping
With chopping enabled, the multiplexer repeatedly reverses the
ADC inputs. Every output data result is then calculated as an
average of two conversions, the first with the positive and the
second with the negative offset term included. This effectively
removes any offset error of the input buffer and sigma-delta
modulator.
However, chopping is applied only behind the input resistor
divider stage; therefore, chopping does not eliminate the offset
error and drifts caused by the resistors. Figure 24 shows the
channel signal chain with chopping enabled.
+
-
DIGITAL
INTERFACE
CHOP
CHOP
f
MCLK
/2
f
MCLK
/2
BUFFER
MULTIPLEXER
DIGITAL
FILTER
SCALING
ARITHMETIC
(CALIBRATIONS)
OUTPUT DATA
AT THE SELECTED
DATA RATE
AIN(+)
AIN(–)
BIAS(+)
BIAS(–)
Σ
MODULATOR
Figure 24. Channel Signal Chain Diagram with Chopping Enabled
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