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參數(shù)資料
| 型號(hào)： | AD7732 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 2-Channel, +-10 V Input Range, High Throughput, 24-Bit SIGMA- ADC |
| 中文描述： | 2通道，-10 V輸入范圍，高通量，24位Σ-模數(shù)轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 20/32頁(yè) |
| 文件大?。?/td> | 1576K |
| 代理商： | AD7732 |
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AD7732
Mode Register
8 Bits, Read/Write Register, Address 38h, 3Ah, Default Value 00h
The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets
the RDY pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits.
The AD7732 contains only one mode register. Bit 1 of the address is used for writing to the mode register to specify the channel selected
for the operation determined by the MD2 to MD0 bits. Only the address 38h must be used for reading from the mode register.
Bit
Mnemonic
Default
Bit 7
MD2
0
Bit 6
MD1
0
Bit 5
MD0
0
Bit 4
CLKDIS
0
Bit 3
DUMP
0
Bit 2
Cont RD
0
Bit 1
24/16 BIT
0
Bit 0
CLAMP
0
Bit
7–5
Mnemonic
MD2–MD0
Description
Mode Bits. These three bits determine the AD7732 operation mode. Writing a new value to the mode bits will
exit the part from the mode in which it has been operating and place it in the newly requested mode
immediately. The function of the mode bits is described in more detail below.
Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the
MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a
power saving feature. When using an external clock on MCLKIN, the AD7732 continues to have internal clocks
and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic
resonator across the MCLKIN and MCLKOUT pins, the AD7732 clock is stopped and no conversions can take
place when the CLKDIS bit is active. The AD7732 digital interface can still be accessed using the SCLK pin.
DUMP Mode. When this bit is reset to 0, the channel status register and channel data register will be
addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed
immediately by a read of the channel data register regardless of whether the status or data register has been
addressed through the communication register. The continuous read mode will always be dump mode
reading of the channel status and data register, regardless of the dump bit value (see the Digital Interface
Description section for more details).
When this bit is set to 1, the AD7732 will operate in the continuous read mode (see the Digital Interface
Description section for more details).
The Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits
wide. When set to 0, the channel data registers will be 16 bits wide.
This bit determines the channel data register’s value when the analog input voltage is outside the nominal
input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped either
to all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the
CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage
range (see the Analog Input’s Extended Voltage Range section).
4
CLKDIS
3
DUMP
2
Cont RD
1
24/16 BIT
0
CLAMP
MD2
0
0
0
0
1
1
1
1
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
Mode
Idle Mode
Continuous Conversion Mode
Single Conversion Mode
Power-Down (Standby) Mode
ADC Zero-Scale Self-Calibration
For Future Use
Channel Zero-Scale System Calibration
Channel Full-Scale System Calibration
Address Used for Mode Register Write Specifies:
The First Channel to Start Converting
Channel to Convert
Channel Conversion Time Used for the ADC Self-Calibration
Channel to Calibrate
Channel to Calibrate
Rev. 0 | Page 20 of 32
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