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參數(shù)資料
| 型號： | AD7722ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 195KSPS 44-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 220k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 375mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
REV. B
–8–
AD7722
PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
AVDD1
14
Clock Logic Power Supply Voltage for the Analog Modulator, 5 V
± 5%.
AGND1
10
Clock Logic Ground Reference for the Analog Modulator.
AVDD
20, 23
Analog Power Supply Voltage, 5 V
± 5%.
AGND
9, 13, 15, 19, Ground Reference for Analog Circuitry.
21, 25, 26
DVDD
39
Digital Power Supply Voltage, 5 V
± 5%.
DGND
6, 28
Ground Reference for Digital Circuitry.
REF1
22
Reference Input/Output. REF1 connects through 3 k
to the output of the internal 2.5 V reference and
to the input of a buffer amplifier that drives the
Σ-modulator. This pin can also be overdriven with an
external reference 2.5 V.
REF2
24
Reference Input/Output. REF2 connects to the output of an internal buffer amplifier used to drive the
Σ- modulator. When REF2 is used as an input, REF1 must be connected to AGND.
VIN(+)
18
Positive Terminal of the Differential Analog Input.
VIN(–)16Negative Terminal of the Differential Analog Input.
UNI
7Analog Input Range Select Input.
UNI selects the analog input range for either bipolar or unipolar
operation. A logic low input selects unipolar operation. A logic high input selects bipolar operation.
CLKIN
11
Clock Input. Master clock signal for the device. The CLKIN pin interfaces the AD7722 internal
oscillator circuit to an external crystal or an external clock. A parallel resonant, fundamental-frequency,
microprocessor-grade crystal and a 1 M
resistor should be connected between the CLKIN and
XTAL pins with two capacitors connected from each pin to ground. Alternatively, the CLKIN pin
can be driven with an external CMOS compatible clock. The AD7722 is specified with a clock input
frequency of 12.5 MHz.
XTAL
12
Oscillator Output. The XTAL pin connects the internal oscillator output to an external crystal.
If an external clock is used, XTAL should be left unconnected.
P/
S
8
Parallel/Serial Interface Select Input. A logic high configures the output data interface for parallel mode
operation. The serial mode operation is selected with the P/
S set to a logic low.
CAL
27
Calibration Logic Input. A logic high input for a duration of one CLKIN cycle initiates a
calibration sequence for the device gain and offset error.
RESET
17
Reset Logic Input. RESET is used to clear the offset and gain calibration registers. RESET is an
asynchronous input. RESET allows the user to set the AD7722 to an uncalibrated state if the
device had been previously calibrated. A rising edge also resets the AD7722
Σ- modulator by
shorting the integrator capacitors in the modulator. In addition, RESET functions identically to
the SYNC pin described below. When operating with more than one AD7722, a RESET/SYNC
should be issued following power up to ensure the devices are synchronized. Ensure that the
supplies are settled before applying the RESET/SYNC pulse.
CS
29
Chip select is a level sensitive logic input.
CS enables the output data register for parallel mode read
operation. The
CS logic level is sensed on the rising edge of CLKIN. The output data bus is enabled
when the rising edge of CLKIN senses a logic low level on
CS if RD is also low. When CS is sensed
high, the output data bits DB15–DB0 will be high impedance. In serial mode, tie
CS to a logic low.
SYNC
30
Synchronization Logic Input. SYNC is an asynchronous input. When using more than one
AD7722 operated from a common master clock, SYNC allows each ADC’s
Σ- modulator to
simultaneously sample its analog input and update its output data register. A rising edge resets
the AD7722 digital filter sequencer counter to zero. After a SYNC, conversion data is not valid until
after the digital filter settles (see Figure 7). DVAL goes low in the serial mode. When the rising
edge of CLKIN senses a logic low on SYNC (or RESET), the reset state is released; in parallel
mode,
DRDY goes high. After the reset state is released, DVAL returns high after 8192 CLKIN
cycles (128
× 64/f
CLKIN); in parallel mode, DRDY returns low after one additional convolution cycle
of the digital filter (64 CLKIN periods), when valid data is ready to be read from the output data
register. When operating with more than one AD7722, a RESET/SYNC should be issued follow-
ing power up to ensure the devices are synchronized. Ensure that the supplies are settled before
applying the RESET/SYNC pulse.
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| AD7723BSZ | 功能描述:IC ADC 16BIT SIGMA-DELTA 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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