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參數(shù)資料
| 型號： | AD7721ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SIGMA-DELTA 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 468.75k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
AD7721
REV. A
–11–
a linear phase response. This is very difficult to achieve with
analog filters.
Analog filters, however, can remove noise superimposed on the
signal before it reaches the ADC. Digital filtering cannot do this
and noise peaks riding on signals, near full-scale, have the po-
tential to overload the analog modulator even though the aver-
age value of the signal is within limits.
0.0
–50.0
0.5fCLK
–100.0
–150.0
GAIN
–
dB
0.1fCLK
0.2fCLK
0.3fCLK
0.4fCLK
FREQUENCY
0.0fCLK
Figure 9a. 128 Tap FIR Filter Frequency Response
0.0
–50.0
–100.0
–150.0
1.0fCLK/32
0.8fCLK/32
0.6fCLK/32
0.4fCLK/32
0.2fCLK/32
0.0fCLK/32
FREQUENCY
GAIN
–
dB
Figure 9b. 83 Tap FIR Filter Frequency Response
SERIAL INTERFACE
The AD7721’s serial communication port allows easy inter-
facing to industry-standard microprocessors, microcontrollers
and digital signal processors. The AD7721 is operated in self-
clocking mode, the AD7721 providing the serial clock. The
RFS signal is also provided by the AD7721 by tying RFS to
DRDY.
Figure 10 shows the timing diagram for reading from the
AD7721.
DRDY goes high to indicate that a conversion has
been completed.
DRDY remains high for one internal clock
(15 MHz) cycle and then goes low for the next 31 clock cycles.
New data is loaded into the output shift register on the rising
edge of
DRDY. When DRDY goes low, the data is accessed
from the AD7721. Although the AD7721 has a 12-bit digital
output in the parallel mode, sixteen bits of data are available for
transmission in the serial mode, starting with the MSB. Serial
data is clocked out of the device on the rising edge of SCLK
and is valid on the falling edge of SCLK.
CIRCUIT DESCRIPTION
Sigma-Delta ADC
The AD7721 ADC employs a sigma-delta conversion technique
that converts the analog input into a digital pulse train.
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to fCLK/2, the noise energy which is contained
in the band of interest is reduced (Figure 8a). To reduce the
quantization noise further, a high order modulator is employed
to shape the noise spectrum, so that most of the noise energy is
shifted out of the band of interest (Figure 8b).
The digital filter that follows the modulator removes the large
out of band quantization noise (Figure 8c), while converting the
digital pulse train into parallel 12 bit wide binary data or serial
16 bit wide binary data.
BAND OF
INTEREST
QUANTIZATION NOISE
fCLK/2
a.
BAND OF
INTEREST
NOISE
SHAPING
fCLK/2
b.
BAND OF
INTEREST
fCLK/2
DIGITAL FILTER CUTOFF FREQUENCY
WHICH EQUALS 152.8kHz (10MHz) OR
229.2kHz (15MHz)
c.
Figure 8. Sigma-Delta ADC
Digital Filter
The digital filter that follows the modulator removes the large
out of band quantization noise, while converting the one bit
digital pulse train into 12-bit or 16-bit wide binary data. The
digital filter also reduces the data rate from fCLK at the input of
the filter to fCLK/32 at the output of the filter. The output data
rate is a little over twice the signal bandwidth which guarantees
that there is no loss of data in the signal band.
The AD7721 employs 2 FIR filters in series. The first filter is a
128 tap filter that samples the output of the modulator at fCLK.
The second filter is an 83 tap half-band filter that samples the
output of the first filter at fCLK/16 and decimates by 2. The
frequency response of the 2 filters is shown in Figure 9.
Digital filtering has certain advantages over analog filtering.
First, since digital filtering occurs after the A/D conversion, it
can remove noise injected during the conversion process. Ana-
log filtering cannot do this. Second, the digital filter combines
low passband ripple with a steep roll off, while also maintaining
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7721SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7722 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| AD7722AS | 制造商:Rochester Electronics LLC 功能描述:16-BIT SIGMA-DELTA CONVERTER I.C. - Bulk 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD7722AS-ES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD7722ASZ | 功能描述:IC ADC 16BIT 195KSPS 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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