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參數(shù)資料
| 型號： | AD7721ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SIGMA-DELTA 28SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 468.75k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
AD7721
REV. A
–6–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
AVDD
Analog Positive Supply Voltage, +5 V
± 5%.
AGND
Ground reference point for analog circuitry.
DVDD
Digital Supply Voltage, +5 V
± 5%.
DGND
Ground reference point for digital circuitry. DGND must be connected via its own short path to AGND (Pin 24).
DSUBST
This is the substrate connection for digital circuits. It must be connected via its own short path to AGND
(Pin 24).
VIN1
Analog Input. In unipolar operation, the analog input range on VIN1 is VIN2 to (VIN2 + VREFIN); for bipolar
VIN2
operation, the analog input range on VIN1 is (VIN2
± V
REFIN/2). The absolute analog input range must lie
between 0 and AVDD. The analog input is continuously sampled and processed by the analog modulator.
REFIN
Reference Input. The AD7721 operates with an external reference, of value 2.5 V nominal. A suitable refer-
ence for operation with the AD7721 is the AD780. A 100 nF decoupling capacitor is required between
REFIN and AGND.
CLK
CMOS Logic Clock Input. The AD7721 operates with an external clock which is connected to the CLK pin.
The modulator samples the analog input on both phases of the clock, increasing the sampling rate to 20 MHz
(CLK = 10 MHz) or 30 MHz (CLK = 15 MHz).
Serial Mode Only
CS, RD, WR
To select the serial interface mode of operation, the AD7721 must be powered up with
CS, RD and WR all
tied to DGND. After two clock cycles, the AD7721 switches into serial mode. These pins must remain low
during serial operation.
DRDY
In the serial interface mode, a rising edge on
DRDY indicates that new data is available to be read from the
interface. During a synchronization or calibration cycle,
DRDY remains low until valid data is available.
SDATA/DB11
Serial Data Output. Output serial data becomes active after
RFS goes low. Sixteen bits of data are clocked
out starting with the MSB. Serial data is clocked out on the rising edge of SCLK and is valid on the subse-
quent falling edge of SCLK.
RFS/DB10
Receive Frame Synchronization. Active low logic input. This is a logic input with
RFS provided by connect-
ing this input to
DRDY. When RFS is high, SDATA is high impedance.
DB9
This is a test mode pin. This pin must be tied to DGND.
DB8
This is a test mode pin. This pin must be tied to DGND.
SCLK/DB7
Serial Clock. Logic Output. The internal digital clock is provided as an output on this pin. Data is output
from the AD7721 on the rising edge of SCLK and is valid on the falling edge of SCLK.
DB6
This is a test mode pin. This pin must be tied to DGND.
SYNC/DB5
Synchronization Logic Input. A rising edge on
SYNC starts the synchronization cycle. SYNC must be
pulsed low for at least one clock cycle to initiate a synchronization cycle.
DB4
This is a test mode pin. This pin must be tied to DGND.
DB3
This is a test mode pin. This pin must be tied to DGND.
UNI/DB2
Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects
bipolar mode.
CAL/DB1
Calibration Mode Logic Input. CAL must go high for at least one clock cycle to initiate a calibration cycle.
STBY/DB0
Standby Mode Logic Input. A logic high on this pin selects standby mode.
DVAL/
SYNC
Data Valid Digital Output. In serial mode, this pin is a dedicated data valid pin.
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| AD7722ASZ | 功能描述:IC ADC 16BIT 195KSPS 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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