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參數(shù)資料
| 型號： | AD7682 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 8-Channel, 250 kSPS PulSAR㈢ ADC. |
| 中文描述： | 16位，8通道，250 kSPS的PulSAR系列㈢ADC的。 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 2041K |
| 代理商： | AD7682 |
Preliminary Technical Data
AD7689
WITHOUT BUSY INDICATOR
This mode is usually used when the AD7689 is connected to an
SPI-compatible digital host. The connection diagram is shown
in Figure 17, and the corresponding timing is given in Figure
18.
A rising edge on CNV initiates a conversion and forces SDO to
high impedance. Once a conversion is initiated, it continues
until completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator.
Configuring the AD7689 for the (n + 1) conversion is initiated
when SCK is high and a rising edge on CNV. After this mode is
initiated, CNV is a don’t care as the CFG word is written in
MSB first with 14 SCK rising edges. As shown in Figure 18,
CFG is written to during the current (
n
) conversion before the
end of conversion, or t
CONV
minimum time. At the end of
Rev. PrC | Page 17 of 20
conversion, the register is updated. In this mode, the new
configuration settings are used for the following (n + 1)
acquisition and conversion. The AD7689 can also be
configured on 14 SCKs of the data reading (not shown), thus
reducing the number of SCK bursts. However, this new CFG
setting is for the (n + 2) conversion since the (
n
) conversion has
ended. This mode is useful when using multiple AD7689s using
the same configuration.
When the conversion is complete, the AD7689 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
th
SCK falling edge or when CNV goes high (whichever
occurs first), SDO returns to high impedance.
DATA IN
CFG DATA
CLK
CONVERT
CNV
SCK
SDO
DIN
AD7689
DIGITAL HOST
-
Figure 17. Without Busy Indicator Connection Diagram
D15
D14
D13
D2
D1
t
DIS
SCK
1
2
3
1
2
3
13
14
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
SDIN
t
HDIN
t
CSCK
CONVERSION
(n)
CONVERSION
(n + 1)
ACQUISITION
(n)
ACQUISITION
(n + 1)
t
CONV
t
CYC
t
CNVH
t
ACQ
t
EN
CNV
14
15
16
D0
DIN
SDO
C13
C12
C11
C1
C0
Figure 18. Without Busy Indicator Serial Interface Timing
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