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參數(shù)資料
| 型號： | AD7680BRMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT LP UNIPOLR 8MSOP |
| 標準包裝： | 3,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 26.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD7680
Rev. A | Page 17 of 24
SERIAL INTERFACE
Figure 20 shows the detailed timing diagram for serial
interfacing to the AD7680. The serial clock provides the
conversion clock and also controls the transfer of information
from the AD7680 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state, and samples the analog input.
The conversion is also initiated at this point and requires at least
20 SCLK cycles to complete. Once 17 SCLK falling edges have
elapsed, the track-and-hold goes back into track mode on the
next SCLK rising edge. Figure 20 shows a 24 SCLK transfer that
allows a 100 kSPS throughput rate. On the 24th SCLK falling
edge, the SDATA line goes back into three-state. If the rising
edge of CS occurs before 24 SCLKs have elapsed, the conversion
terminates and the SDATA line goes back into three-state;
otherwise SDATA returns to three-state on the 24th SCLK
falling edge as shown in Figure 20.
A minimum of 20 serial clock cycles are required to perform
the conversion process and to access data from the AD7680.
CS going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges beginning with the second
leading zero; thus the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the
second leading zero. If a 24 SCLK transfer is used as in Figure 20,
the data transfer consists of four leading zeros followed by the
16 bits of data, followed by four trailing zeros. The final bit
(fourth trailing zero) in the data transfer is valid on the 24th
falling edge, having been clocked out on the previous (23rd)
falling edge. If a 20 SCLK transfer is used as shown in Figure 21,
the data output stream consists of only four leading zeros
followed by 16 bits of data with the final bit valid on the 20th
SCLK falling edge. A 20 SCLK transfer allows for a shorter cycle
time and therefore a faster throughput rate is achieved.
03643-0-013
tQUIET
tCONVERT
t1
t8
t7
t5
t6
t3
t4
4 LEADING ZEROS
3-STATE
0
ZERO
DB15
DB1
DB0
ZERO
SCLK
1234
5
18
19
20
21
22
23
24
SDATA
4 TRAILING ZEROS
CS
t2
Figure 20. AD7680 Serial Interface Timing Diagram—24 SCLK Transfer
03643-0-014
tQUIET
t6
t5
t7
t8
t4
t3
tCONVERT
t2
t1
0
ZERO
DB15
DB1
DB0
SCLK
12
34
5
18
19
20
SDATA
CS
4 LEADING ZEROS
3-STATE
Figure 21. AD7680 Serial Interface Timing Diagram—20 SCLK Transfer
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