參數(shù)資料
型號(hào)： AD7680BRMZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT LP UNIPOLR 8MSOP
標(biāo)準(zhǔn)包裝： 3,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 100k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 26.4mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
AD7680
Rev. A | Page 13 of 24
ADC TRANSFER FUNCTION
The output coding of the AD7680 is straight binary. The
designed code transitions occur at successive integer LSB
values, i.e., 1 LSB, 2 LSBs. The LSB size is VDD/65536. The ideal
transfer characteristic for the AD7680 is shown in Figure 14.
03643-0-007
000...000
111...111
1 LSB = VDD/65536
1 LSB
+VDD–1 LSB
ANALOG INPUT
0V
000...001
000...010
111...110
111...000
011...111
Figure 14. AD7680 Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 15 shows a typical connection diagram for the AD7680.
VREF is taken internally from VDD and as such should be well
decoupled. This provides an analog input range of 0 V to VDD.
The conversion result is output in a 24-bit word, or alternatively,
all 16 bits of the conversion result may be accessed using a
minimum of 20 SCLKs. This 20-/24-bit data stream consists of
a four leading zeros, followed by the 16 bits of conversion data,
followed by four trailing zeros in the case of the 24 SCLK
transfer. For applications where power consumption is of
concern, the power-down mode should be used between
conversions or bursts of several conversions to improve power
performance (see the Modes of Operation section).
In fact, because the supply current required by the AD7680 is so
low, a precision reference can be used as the supply source to
the AD7680. For example, a REF19x voltage reference (REF195
for 5 V or REF193 for 3 V) or an AD780 can be used to supply
the required voltage to the ADC (see Figure 15). This
configuration is especially useful if the power supply available is
quite noisy, or if the system supply voltages are at some value
other than the required operating voltage of the AD7680, e.g.,
15 V. The REF19x or AD780 outputs a steady voltage to the
AD7680. Recommended decoupling capacitors are a 100 nF low
ESR ceramic (Farnell 335-1816) and a 10 μF low ESR tantalum
(Farnell 197-130).
03643-
0-
008
AD7680
0V TO VDD
INPUT
VIN
SCLK
SDATA
SERIAL
INTERFACE
C/P
CS
VDD
GND
10
F
TANT
0.1
F
3V
10
F
0.1
F
5V
SUPPLY
REF193
Figure 15. Typical Connection Diagram
Digital Inputs
The digital inputs applied to the AD7680 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted by the
VDD + 0.3 V limit as on the analog inputs. For example, if the
AD7680 were operated with a VDD of 3 V, 5 V logic levels could
be used on the digital inputs. However, it is important to note
that the data output on SDATA still has 3 V logic levels when
VDD = 3 V.
Another advantage of SCLK and CS not being restricted by the
VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If one of these digital inputs is applied before VDD, then
there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V were applied prior to VDD.
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