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參數資料
| 型號： | AD7680BRMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT LP UNIPOLR 8MSOP |
| 標準包裝： | 3,000 |
| 系列： | PulSAR® |
| 位數： | 16 |
| 采樣率（每秒）： | 100k |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 26.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 1 個單端，單極 |
AD7680
Rev. A | Page 15 of 24
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered
down between each conversion, or a series of conversions may
be performed at a high throughput rate, and then the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7680 is in
power-down, all analog circuitry is powered down.
To enter power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the 10th falling edge of SCLK
as shown in
. Once
CS has been brought high in this
window of SCLKs, the part enters power-down, the conversion
that was initiated by the falling edge of CS is terminated, and
SDATA goes back into three-state. If CS is brought high before
the second SCLK falling edge, the part remains in normal mode
and will not power down. This avoids accidental power-down
due to glitches on the CS line.
In order to exit this mode of operation and power up the
AD7680 again, a dummy conversion is performed. On the
falling edge of CS, the device begins to power up and continues
to power up as long as CS is held low until after the falling edge
of the 10th SCLK. The device is fully powered up once at least
16 SCLKs (or approximately 6 μs) have elapsed and valid data
results from the next conversion as shown in
. If
CS is
brought high before the 10th falling edge of SCLK, regardless of
the SCLK frequency, the AD7680 goes back into power-down
again. This avoids accidental power-up due to glitches on the
CS line or an inadvertent burst of 8 SCLK cycles while CS is low.
So although the device may begin to power-up on the falling
edge of CS, it powers down again on the rising edge of CS as
long as it occurs before the 10th SCLK falling edge.
03643-0-010
SCLK
SDATA
1
2
10
20
THREE-STATE
CS
Figure 17. Entering Power-Down Mode
03643-0-011
110
20
1
20
SDATA
SCLK
CS
INVALID DATA
VALID DATA
THE PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
THE PART BEGINS
TO POWER UP
tPOWER UP
Figure 18. Exiting Power-Down Mode
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