參數(shù)資料
型號： AD7674ACPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 24/28頁
文件大?。?/td> 0K
描述： IC ADC 18BIT SAR 5V 48LFCSP
產(chǎn)品培訓模塊： ADC Applications
ADC Architectures
ADC DC/AC Performance
標準包裝： 2,500
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 800k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 138mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應商設備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，雙極
配用： EVAL-AD7674CBZ-ND - BOARD EVALUATION FOR AD7674
AD7674
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figure 34 and Figure 35
Convert Pulsewidth
t1
10
ns
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1
t2
1.25/1.5/1.75
μs
CNVST LOW to BUSY HIGH Delay
t3
35
ns
BUSY HIGH All Modes Except Master Serial Read after Convert
(Warp Mode/Normal Mode/Impulse Mode)
t4
1/1.25/1.5
μs
Aperture Delay
t5
2
ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
t7
1/1.25/1.5
μs
Acquisition Time
t8
250
ns
RESET Pulsewidth
t9
10
ns
Refer to Figure 36, Figure 37, and Figure 38 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode)
t10
1/1.25/1.5
μs
Data Valid to BUSY LOW Delay
t11
20
ns
Bus Access Request to Data Valid
t12
45
ns
Bus Relinquish Time
t13
5
15
ns
Refer to Figure 40 and Figure 41 (Master Serial Interface Modes) 2
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode)
t17
25/275/525
ns
SYNC Asserted to SCLK First Edge Delay3
t18
3
ns
Internal SCLK Period3
t19
25
40
ns
Internal SCLK HIGH3
t20
12
ns
Internal SCLK LOW3
t21
7
ns
SDOUT Valid Setup Time3
t22
4
ns
SDOUT Valid Hold Time3
t23
2
ns
SCLK Last Edge to SYNC Delay3
t24
3
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert3
t28
Table 4
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
t29
1/1.25/1.5
μs
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figure 42 and Figure 43 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5
ns
External SCLK Active Edge to SDOUT Delay
t32
3
18
ns
SDIN Setup Time
t33
5
ns
SDIN Hold Time
t34
5
ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
1In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7674AST 制造商:Analog Devices 功能描述:ADC Single SAR 800ksps 18-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:18-BIT,800KSPSSARADC - Tape and Reel 制造商:Analog Devices 功能描述:IC 18-BIT ADC
AD7674ASTRL 制造商:Analog Devices 功能描述:ADC Single SAR 800ksps 18-bit Parallel/Serial 48-Pin LQFP T/R
AD7674ASTZ 功能描述:IC ADC 18BIT 800KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
AD7674ASTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC
AD7674ASTZL 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC
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