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參數(shù)資料
| 型號： | AD7674ACPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT SAR 5V 48LFCSP |
| 產(chǎn)品培訓模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標準包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 800k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 138mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7674CBZ-ND - BOARD EVALUATION FOR AD7674 |
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AD7674
Rev. A | Page 22 of 28
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
12
3
16
17
18
D17
D16
D2
D1
D0
X
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t14
t20
t15
t16
t22
t23
t29
t28
t18
t19
t21
t30
t25
t24
t26
t27
03083-0-040
Figure 40. Master Serial Data Timing for Reading (Read after Convert)
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
D17
D16
D2
D1
D0
X
12
3
16
17
18
BUSY
SYNC
SCLK
SDOUT
CS, RD
CNVST
t3
t1
t17
t14
t15
t19
t20
t21
t16
t22
t23
t24
t27
t26
t25
t18
EXT/INT = 0
03083-0-046
Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
SLAVE SERIAL INTERFACE
External Clock
The AD7674 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 42 and Figure 43 show the detailed timing
diagrams of these methods.
While the AD7674 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
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| AD7675ACPZ | IC ADC 16BIT SAR 100KSPS 48LFCSP |
| AD7676ASTZRL | IC ADC 16BIT DIFF INP 48LQFP |
| AD7677ACPZ | IC ADC 16BIT DIFF INP 48-LFCSP |
| AD7678ACPZ | IC ADC 18BIT SAR W/BUFF 48LFCSP |
| AD7679ACPZ | IC ADC 18BIT SAR W/BUFF 48LFCSP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7674AST | 制造商:Analog Devices 功能描述:ADC Single SAR 800ksps 18-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:18-BIT,800KSPSSARADC - Tape and Reel 制造商:Analog Devices 功能描述:IC 18-BIT ADC |
| AD7674ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 800ksps 18-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7674ASTZ | 功能描述:IC ADC 18BIT 800KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7674ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC |
| AD7674ASTZL | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC |
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